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MSP432P401R: Question on I2C interfacing

robert schaefer
Expert 2050 points

Part Number: MSP432P401R

I'm writing to a TCA9548A over the I2C bus using a MSP432P401R as a master. The write is the standard start bit followed by the

seven address bits 0x70 followed by a 0 (low) for a write. At this point I expect a ACK from the TCA9548A and get one about

26mS later which is then followed by the data 0x01 (which should enable channel 0) , followed by an ACK and a STOP.

While this seems to be working, when reading back the control register data it read 0x00 and when testing the I2C bus

on the channel 0 output it is not connected through the TCA9548A chip to the output.

1. Is the 26 ms delay of the first ACK an valid example of clock stretching?

2. Are there any things to be aware of when using the TCA9548A (this is a TI chip), i.e. why would it ack but not connect to the output?

  • 0
    TI__Guru 57351 points
    I will need to reach out to one of the product experts. I will touch base again on Monday.

    Chris
  • 0
    TI__Guru 63000 points

    Hey Robert,

    Can you provide the schematic for the TCA9548A and some o-scope shots so we can verify the signal looks okay first? I'll be able to see if there is anything unusual from taking a look at that.

    1. Is the 26 ms delay of the first ACK an valid example of clock stretching?
    -You shouldn't see clock stretching from this device. Is there anything between the TCA9548A and the master? (like a translator/buffer ect.)

    2. Are there any things to be aware of when using the TCA9548A (this is a TI chip), i.e. why would it ack but not connect to the output?
    -I personally have not seen problems with this device. There is no errata for this device besides its POR requirements. (you can find this in section 10 of the datasheet).

    Thanks,
    -Bobby

  • 0 in reply to BOBBY
    TI__Mastermind 21575 points
    Hello Robert,
    Are you generating a STOP condition after you write the register? The register is loaded when you get an ACK but the command isn't initiated until the STOP condition is generated. Can you confirm this fixes you problem.
    -Francis Houde
  • 0 in reply to fhoude
    Expert 2050 points

    Just saw this now. I'm forwarding this to my hardware teammate to study/reply/ add info to your comments.

  • 0 in reply to fhoude
    Expert 2050 points
    The stop is indeed being generated. We're using a saleae bus analyzer to capture the interaction.
  • 0 in reply to robert schaefer
    Expert 2050 points

    Hooked  up bus pirate and got the systems engineer involved. The problem appears to be the specification/interpretation of the i2c address.

    The spec said to write to address 0x60 but 0x30 (the address prior to shift left) was what was really meant. 

    Just a typical day in the lab :-)

  • 0 in reply to robert schaefer
    TI__Guru 62920 points
    Robert,

    We're glad to hear things are working now! Just let us know if you encounter any issues going forward.

    Max
  • 0 in reply to Miguel Robertson
    Expert 2050 points

    Thank you.

    Even when you don't "actively" help, having a place to write things/describe a problem in detail helps too.

    bob s.