Hi, I just started working today on a problematic board previously designed, but it's high priority and I need to attack from several angles. Issues with intermittent FCS errors on TX and so far only noted in the switch. Working on more data.
First, if someone could please take a quick look at the schematic, that would be great (below).
Known issues/concerns:
- The top of C519 and C520 should have been connected, correct?
- Any idea why are R517 and R518 are not 49.9 ohm. Bizarre. Any theories? Regardless, I will change. Just curious if they are ever not 49.9 for any reason, such as signals not routed as 100 ohm differential.
- Datasheet calls out 10uF PFBOUT cap as tantalum, and we have a ceramic capacitor with much lower ESR than perhaps intended. Do you have a recommended specification here? Will X5R MLCC not work better? What is the PFBIN rail for?
- Not shown in schematic, but we have the same 50MHz reference clock feeding both the reference here on pin 34, and the RMII interface on a STM32F MCU, without a fanout buffer, and poorly routed. For future circuit improvement, do those two reference clocks have to be aligned, or could they be separate 50MHz oscillators with 50ppm or better?
I hope to post for some help tomorrow on layout concerns, and start the process of some loopback tests from a traffic generator.
One other initial oddity: a test engineer did some work with a differential probe on the signals.
TDP3500 - Differential probe,
TDSET3 – Ethernet compliance test automation software
Transmit waveform on TX lines looks like this
:While transmit on the RX lines looks like this:
Any ideas for the poor shape? Is the center hitch from reflection? Sorry, I don't know where probe was placed. The first image also looks perhaps like poor length matching?
Thank you.
