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Original question:

SN65DSI86: SN65DSI86 eDP source PHY test

SN65DSI86: SN65DSI86 eDP source PHY test

user4760726
Intellectual 1195 points
Part Number: SN65DSI86
Other Parts Discussed in Thread: TEST2

Hi Team, 

One of our customers is asking for the tools and configuration setting on SN65DSI86 while doing eDP compliance test. I searched on E2E and found this thread is related to my questions. However, I don't get why panel's EDID is needed for the compliance test. Could you explain about it? Also, is there a procedure to know how to set up SN65DSI86 in term of register setting for eDP compliance test? Please advised. 

Best Regards, 

Leroy 

  • 0
    TI__Guru 64326 points
    Leroy,

    The panel's EDID is needed to configure the other SN65DSI86 registers for the particular panel. To clarify section 8.4.5.12 and 8.4.5.12.1 of the datasheet specify how to generate the compliance patterns but the number of lanes used, clock rate, and other registers must still be set for the particular application (EDID Information). Steps to generate the HBR 2 compliance eye are listed under Table 15 in the datasheet.

    Here are some general steps for the HBR 2 Complaince Pattern:

    1) TEST2 pin is pulled up.
    2) Reg Add:0xFFh set to “07”
    3) Reg Add:0x16h set to “01”
    4) Reg Add:0xFFh set to“00”
    5) Reg Add:0x5A[0] set to 0
    6) Reg Add:0x96h set to “0110”

    Also, for compliance testing, software will need to change the pre-emphasis settings.