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Original question:

DS90UB948-Q1: DS90UB948

DS90UB948-Q1: DS90UB948

Qianqian
Genius 5010 points
Part Number: DS90UB948-Q1

Hello,TI Experts,

I have below questions about DS90UB948 need your help:

1.What's the meaning of T1 and T2 in  Power sequence~

Is it T1 for VDDIO delay time ,T2 for VDD12 delay time ?

2.How to understand active vedio?If the resolution is wrong, will there be a lock signal?

figure 2

3.Is their pattern inside DS90UB948,when their is no LVDS input signal,Will it output the default image?

4.How does CDC host reset DS90UB948 by HSD ? is it by PDB pin？ How to make it?

5.Can I use only one LDO for both VDDIO and VDD33， use Bead to isolate them?

6.Their is High Speed back channel in MODE_SEL1, Does it mean the FPDLINK's transmission rate?

figure 3

7.What's the meaning of PIN1(Lock)? What should the MCU feedback to the output signal?

8. Is PIN4(BISTC) a channel of CLOCK signal？MCU must provide a channel of reference clock,then it can self test?

 

Looking foward to your raply,thank you very much~

  • 0 in reply to Qianqian
    TI__Genius 10475 points
    Hello,

    1. T1 and T2 are the VDD33 to VDDIO and VDD33 to VDD12 ramp delay times. Refer to Fig 15 in the datasheet for the power sequence diagram. A min value of zero means the the supplies may be ramped simultaneously.
    2. RX_LOCK_MODE controls the conditions for RX_LOCK. If this is '1', the lock will be asserted when device is linked to serializer even if active video is not being sent.
    3. There is pattern generator inside 948 that you can enable.
    4. You can use PDB or digital reset to issue the reset. Refer to the datasheet for more information.
    5. Same supply can be used for both VDD33 and VDDIO and ramped simultaneously but make sure proper bypass capacitors and ferrite beads are used.
    6. No this refers to the backchannel rate. The low speed control channel from the deserializer to the serializer.
    7. LOCK indicates the deserializer has locked to the incoming data stream.
    8. The BIST test may select either an external PCLK or the 33 MHz internal clock in the Ser. In the absence of PCLK the user can select the internal oscillator frequency at the Des through the BISTC pin or BIST configuration register.