• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 3 answers
  • Subscribers 34 subscribers
  • Views 675 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

Linux/DS90UB940-Q1: Ds90ub940-q1 mipi clk output is only 33K

Linux/DS90UB940-Q1: Ds90ub940-q1 OUTPUT ENABLE The default is 0 after power on

user4823313
Prodigy 230 points

Part Number: DS90UB940-Q1

Tool/software: Linux

hello 

1.why ds90ub940-q1 output enable default is 0 after power on

2.After manually enabling output 0x02=0x90  and 0x6c =0x02 0x6d=0x83 ipu=0 csi=0 vc=0

mipi clk mipi_csi2_write(info, 0x00000044, 0x4a) (372M)

./mxc_v4l2_capture.out -iw 640 -ih 480

v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0 ？？？？？？??

my design  imx6d+947+940 Pass lock is high in bist mode and normal mode 

please help me 

  • 0
    TI__Mastermind 30515 points

    Shiyong,

    regarding the output status of UB940, please check d/s page25 (table2, output state table), they are controlled by PDB pin and the reg. 0x02.

    For the CSI_EN_Port0/1 is disabled in default, please see d/s in page66 (table13). may I know why you configure " 0x6c =0x02 0x6d=0x83"?

    best regards,

    Steven

  • 0 in reply to Steven(Shenzhen) Shi
    Prodigy 230 points

    hi Steven
    1.I want to know what X Z HS0 is in table 25 on page 25.

    2.My current situation is PDB (H) OUTPUT ENABLE (L) OUTPUT SLEEP (L) LOCK (H) PASS (H) why? and how to PDB(H) OUTPUT ENABLE(H)

    3. " 0x6c =0x02 0x6d=0x83" is page 16 (4)(d) 640x480p60; PCLK = 25MHz; 2 MIPI lanes reg0x6c=0x02; reg0x6d=0x83

    4.and enable csi port 0 ./i2cset -f -y 0 0x2c 0x6c 0x13 ./i2cset -f -y 0 0x2c 0x6d 0x3f correct??

    No size specified (using byte-data access)
             0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
    00: 58 04 00 f0 fe 1e 00 34 00 00 00 00 00 00 00 00 X?.???.4........
    10: 00 00 00 00 00 00 00 00 00 01 00 00 23 40 00 00 .........?..#@..
    20: 00 00 40 20 08 00 83 84 01 00 00 00 00 00 00 00 ..@ ?.???.......
    30: 00 00 90 25 01 00 00 8a 00 00 00 00 20 e0 23 00 ..?%?..?.... ?#.
    40: 43 03 03 00 60 88 00 00 0f 00 00 08 00 00 63 00 C??.`?..?..?..c.
    50: 03 10 00 01 80 00 00 00 00 7f 20 20 00 00 00 00 ??.??....? ....
    60: 00 00 00 00 10 00 00 00 00 00 00 00 00 03 00 00 ....?........?..
    70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00 ...???......?...
    80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    a0: 00 00 84 00 00 00 00 00 00 00 00 00 00 00 00 00 ..?.............
    b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 ........?.......
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    f0: 5f 55 42 39 34 30 00 00 00 00 00 00 00 00 00 00 _UB940..........

    best regards,

  • 0 in reply to user4823313
    TI__Mastermind 30515 points
    Hi, please check below feedbacks:
    1.I want to know what X Z HS0 is in table 25 on page 25.
    --> X: anything; Z: high impedance; HS0: High speed low level

    2.My current situation is PDB (H) OUTPUT ENABLE (L) OUTPUT SLEEP (L) LOCK (H) PASS (H) why? and how to PDB(H) OUTPUT ENABLE(H)
    -> you can check the Pass pin external circuit? can it be right?

    3. " 0x6c =0x02 0x6d=0x83" is page 16 (4)(d) 640x480p60; PCLK = 25MHz; 2 MIPI lanes reg0x6c=0x02; reg0x6d=0x83
    --> please confirm your video resolution is 640x480, and PCLK is 25MHz?

    4.and enable csi port 0 ./i2cset -f -y 0 0x2c 0x6c 0x13 ./i2cset -f -y 0 0x2c 0x6d 0x3f correct??
    --> please refer to d/s page39 on mode_sel0/1 setting to select the correct CSI2 port and lane number (mode_sel0=#3, mode_sel1 = #1 if designed for STP).

    best regards,
    Steven