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Original question:

DS80PCI102: Can DS80PCI102 used with PCIe Gen3 two lane application ?

DS80PCI102: PCIe retimer for Gen3/2 x2 applicatoin

Andy Jackson
Prodigy 70 points
Part Number: DS80PCI102
Other Parts Discussed in Thread: DS80PCI800, DS80PCI402, DS125BR401A

Hi - this is related to the post "DS80PCI102: Can DS80PCI102 used with PCIe Gen3 two lane application ?".

I'm in need of a retimer for PCIe Gen 3 and 2, x2 only, connecting to a Pericom PI2EQX5804 over an iPass cable.  I'm a little confused about which parts will support that application.

I see the DS80PCI102 single lane (2 channel) device and presume I could use two of those to support a x2 link.  Is that correct?

I also see the DS80PCI402 and DS80PCI800 devices, but from the documentation I can't definitively glean if they will support a x2 only link, or what the advantage may be over two x1 devices (board space only?).

Could you please offer some guidance for my application?

Also, are any of these parts configurable for both upstream and downstream applications?  That is, the same board will be used either next to the Endpoint (I call downstream application), or next to the Root Complex (upstream application), so I need to be able to configure the retimer so it knows where to expect the Root Complex's training patterns (port A or port B).

Thank you,

Andy Jackson

  • 0
    TI__Guru* 93670 points
    Hi Andy,

    DS80PCI402, DS80PCI102, and DS80PCI800 all are capable of passing analog link training information between PCIe source and sink end point. These devices use the same core but each support different PCIe port. So overall link performance is the same.

    Please note DS125BR401A can be used for upstream and downstream.

    One thing that could help us to point out appropriate device is if you can please provide a block diagram of your system with insertion loss budget at each point. Also, point out where PCI redriver would be used. Distance/insertion loss between transmitter and device could have a big impact as well.

    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    Prodigy 70 points
    Hi Nasser - thanks for the reply and sorry for my delay.

    My main concern is with x2 capability - will any/all of these devices support a x2 only link (Gen 2, Gen 3)?

    We're early in the architecture phase so I don't have a loss budget, but in essence we'll be connecting two retimers over an iPass cable of 1-2m. The other side of the retimers will go to PCIe bridges over ~ 12" of PCB trace and a connector pair.

    Thanks,

    Andy
  • 0 in reply to Andy Jackson
    TI__Mastermind 43795 points

    Andy,

    There devices do not snoop at PCIe protocol so any link width is fine.  They do perform Rx-Detection on a per channel basis to account for the possibility of different link widths.

    Regards,

    Lee

  • 0 in reply to Lee Sledjeski
    Prodigy 70 points

    Thanks Lee - I know this is nit-picky, but is there something in the document that clearly states this?  Wondering if I'm missing it, or if it's just implied by saying that PCIe is supported.

    Thanks,

    Andy

  • 0 in reply to Andy Jackson
    TI__Mastermind 43795 points

    Andy,

    There is nothing in the document which specifically states that receiver detect is done on each channel independently.  It is implied by the table controls which use "input" in a singular context.  Also the register controls are duplicated for each channel.

    All of these devices can support x1 / x2 / x4 / x8 / x16 link widths.  For the larger widths multiple devices will be needed to handle all the channels. 

    Regards,

    Lee

  • 0 in reply to Lee Sledjeski
    Prodigy 70 points
    Ah, thanks for the clarification.

    Last Q, I think I know the answer but want to confirm: do these devices need to know or care which end of the link they are on (e.g. closest to RC, or closest to EP)?

    I presume not, given your statement about them not snooping the protocol, and your colleague's statement about passing the link training information.

    Andy
  • 0 in reply to Andy Jackson
    TI__Mastermind 43795 points
    Hi Andy,

    They do not care either way. I would make sure that you do not place them right next to the RC or EP Tx pins. This will lead to an over-equalized waveform and increase the jitter.

    Regards,
    Lee
  • 0 in reply to Lee Sledjeski
    Prodigy 70 points
    Thanks Lee!

    Regards,
    Andy