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Original question:

DP83867CS: STRAP Pins

DP83867CS: STRAP Pins

DEEPAK V14
Intellectual 810 points
Part Number: DP83867CS

Hi,
The DP83867CS PHY will be used as a normal SGMII interface. The VDDIOx supply is powered with 2.5Volt.

The datasheet suggests that while strap configuration, LED-0 has to be kept in  MODE-2 to enable PHY in SGMII mode during power up.

Q1. Which is the recommended schematics for connecting LED-0, Method1 or Method2? Kindly sugesst.

Q2. If Method2 is chosen is there any specific requirement to be followed while selecting the transistor, like 'Vbe of transistor should be greater than 0.191 x VDDIO (= 0.4775V)' etc..?

Q3. The Transmit, Receive and Clock lines in SGMII mode is having AC copling capcitor. In PCB layout, during placement which is the preffered position to keep these capcitors? Is it nearer to 'PHY' or or is it nearer to the 'FPGA(MAC)'?

Regards
DEEPAK V

  • 0
    TI__Mastermind 19780 points
    Hi Deepak V,

    Q1. Method 1 will work for 2.5V and 3.3V VDDIO. Method 2 is suggested for 1.8V VDDIO only.

    Q3. It depends on the direction and the FPGA guidelines. For example, we recommend the AC coupling cap be close to the transmitter. For the PHY, its RX pairs are the transmitter, so the RX signal AC coupling caps should be close to the PHY. The TX signal AC coupling caps should be close to the FPGA. But please follow the recommendations of the FPGA for AC coupling caps on SerDes pairs as there may be a different suggestion for the TX pairs.

    Best Regards,