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Original question:

SN65DSI 83, Help me!

Linux/SN65DSI84: CHA_SYNCH error

yaqiang jiang
Prodigy 80 points
Other Parts Discussed in Thread: SN65DSI84, DSI-TUNER, SN65DSI85

Tool/software: Linux

HI anyone:

I have got a problem with porting SN65DSI84. 

It shows the error in 0xE5: CHA_SYNCH_ERR. 

And the test pattern is ok. I have checked the data pin from CPU, they should be no problem.

What will the possible cause ?

What does the error means ? it meens NO HSS/VSS package or the package is wrong ?

And another questions:

1. the chip support two video mode: burst and non-burst mode, how to set it ? or does it auto detect ?

2. In the datasheet bit5 to bit7 of the register of 0x10 is "reserved" , but they have some meaning . Does TI have new datasheet ？

I also find some other error in the datasheet , example: 0x18: bit3/2 

  • 0
    TI__Guru**** 393215 points
    What processor is this? What software? Which version?
  • 0 in reply to Biser Gatchev-XID
    Prodigy 80 points

    HI :

    Thanks for you reply.

    I'm using imx8mq, yocto, linux-4.9.51 .

    The attach file: register init generate by "DSI Tuner 2.0.exe" and the lcd I'm using.

    15inch-LCD M150GNN2 R1 [IVO].pdf

  • 0 in reply to yaqiang jiang
    Prodigy 80 points

    sorry , missing the register init file.

    Fullscreen reg_init.txt Download 
    //=====================================================================
// Filename   : m150g_notest.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x05
0x0B              0x10
0x0D              0x00
0x10              0x26
0x11              0x00
0x12              0x27
0x13              0x00
0x18              0x78
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0x00
0x21              0x04
0x22              0x00
0x23              0x00
0x24              0x00
0x25              0x00
0x26              0x00
0x27              0x00
0x28              0x21
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x20
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x0c
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0xa0
0x35              0x00
0x36              0x00
0x37              0x00
0x38              0x00
0x39              0x00
0x3A              0x00
0x3B              0x00
0x3C              0x00
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

  • 0 in reply to yaqiang jiang
    TI__Mastermind 35130 points
    Hi yaqiang,

    Can you please attach the .dsi file?

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Prodigy 80 points

    Hi I.K

    please reference to the attachment.dts.zip

  • 0 in reply to yaqiang jiang
    TI__Mastermind 35130 points

    Hi yaqiang,

    No I mean the .dsi file from the DSI-Tuner configuration. You export it after filling out the parameters. For example:

    Regards,

    I.K.

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 80 points

    HI I.K:

     

    Sorry, my mistake.

    Attach again.

     

    Regards,

    yaqiang15inch.zip

  • 0
    TI__Mastermind 35130 points
    Hi yaqiang,

    In regards to your questions in your original post:

    1. This is a setting on your processor, not something the chip sets.
    2. These bits are reserved for operating modes for the SN65DSI85 (you can check the datasheet) and should not be changed from their default values for the SN65DSI84.
    3. What do you mean by "I also find some other error in the datasheet , example: 0x18: bit3/2"? Please clarify.

    The .dsi file you provided looks correct. I think you are probably not following the initialization sequence on page 15 and 16 of the SN65DSI84 datasheet. Please implement the initialization sequence correctly to see if this resolves your issue.

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    TI__Mastermind 35130 points
    Hi yaqiang,

    If the above post did not solve your issue then please respond with the issue that you are still having.

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Prodigy 80 points
    HI I.K

    It don't resolved my issue. I'm not sure it's the SN65DSI84 or processor's problem.

    2. in "8.6.1.4.1 Register 0x18" , it says 0x10.6:5 is used for LVDS Dual-link or single-link, so it should not be reserved.
    3. in "8.6.1.4.1 Register 0x18", bit3, it says:
    0 – Force 18bpp; LVDS channel A lane 4 (A_Y3P/N) is disabled
    (default)
    1 – Force 24bpp; LVDS channel A lane 4 (B_Y3P/N) is enabled
    but it should be:
    0 – Force 18bpp; LVDS channel A lane 4 (A_Y3P/N) is disabled
    (default)
    1 – Force 24bpp; LVDS channel A lane 4 (A_Y3P/N) is enabled
    right ?

    I did check the initialization sequence, and I implement it by reference to the file of "panel-dsi85.c" using by omap.
  • 0 in reply to yaqiang jiang
    TI__Mastermind 35130 points
    Hi yaqiang,

    2. That is only relevant to the SN65DSI85. Please see register 0x10 in the SN65DSI85 datasheet. The SN65DSI84 does not support those operating modes so those bits are reserved and should not be changed from their default value or the device will not operate correctly.

    3. Correct, that is a typo.

    The 'panel-dsi85.c" is outdated and uses an old, incorrect version of the initialization sequence. Please implement the initialization sequence listed in the datasheet.

    Regards,
    I.K.