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DS90UB948-Q1: timing sequence and I2C control problem

Part Number: DS90UB948-Q1


Dear TI Experts,

I am using DS90UB948, and I met with some problems need your suggestion:

1. As is shown in the picture below, what's the meaning of FRC control? Does it stand for the timing sequence of  the LVDS's signal from DS90UB948?

These are the parameters related to whether the display(I mean the screen)  can work functionally. However, even when some parameters are not set properly, the display can still work functionally. Also, when the parameters( in the red block) are changed dynamically, the display will not change. So I was wondering maybe these register parameter is not for the timing sequence  of theLVDS' s signal from DS90UB948's output to the display.

2. For thise I2C timing sequence parameter(in these two red blocks), I would like to know more details about the timing sequence.

     

The following figure is the requirements for the I2C slave mode  for 948,  I was wondering whether the REG06[3:4] is corresponding to the 'Data hold time'  in the figure below. Also,  what's the parameter that REG05[ 4:6] corresponds to?