SN65DP159: DisplayPort to DisplayPort Retimer Mode Lane Deskew

KT

DP159 does not perform lane to lane skew as a DP retimer. But the inter-pair skew for DP is 2UI, which should not be a problem in the first place.

Thanks
David

Hi David, 

Re: "inter-pair skew for DP is 2UI":

DisplayPort 1.2 spec indicates 20 UI inter-lane skew added at link layer and an additional 4UI + 500ps is allowed at PHY layer: 

PHY Layer:

"Table 3-17: DisplayPort Main Link Transmitter TP2 Parameters"

"LTX-SKEWINTER_PAIR HBR_RBR, Lane-to-Lane Output Skew: 2 UI, Applies to transmitters capable of 2- and 4-lane operation. Applies to all pairwise combinations of supported lanes"

"LTX-SKEWINTER_PAIR HBR2, Lane-to-Lane Output Skew: 4UI + 500ps, Applies to transmitters capable of 2- and 4-lane operation. Applies to all pairwise combinations of supported lanes"

Link Layer: 

"2.2.1.6 Inter-lane Skewing"

"All the symbols, both those transmitted during video display period and those transmitted during video blanking period, are skewed by two LS_Clk period between adjacent lanes"

Regards,

KT

KT

Yes, my answer is based on section 2.2.1.6 of the spec.

Thanks
David

Hi David,
You mentioned 2 UI in your first response. Section 2.2.1.6 is 20 UI of skew between adjacent lanes (two 10-bit symbols) for a total of 60 UI skew for 4 lanes. So is DP159 guaranteed to not interfere the two 10-bit symbol (20 UI) lane-to-lane skew (60 UI total skew) inserted at the link layer ?
Regards,
KT

KT

In the spec, it says "After inserting the Main Link attributes data (and optionally, secondary-data packet), the DisplayPort uPacket
TX must insert a skew of two LS_Clk cycles between adjacent lanes. Figure 2-15 shows how the symbols must
be transported after this inter-lane skewing. All the symbols, both those transmitted during video display
period and those transmitted during video blanking period, are skewed by two LS_Clk period between adjacent
lanes".

The LS_CLK is the link symbol clock which is 540MHz for 5.4G, 270MHz for 2.7G, and 162MHz for 1.6G. The inverse of LC_CLK to me is the same as 1UI.

But the bottom line is the inter-pair skew is a hug number for DP, and I don't see how DP159 can violate this inter-pair skew number.

Thanks
David

Hi David,

1. One LS_CLK is not equal to one UI. One UI is defined as one bit period on the serial link. LS_CLK is defined as one clock cycle of parallel symbol. One LS_CLK cycle equates to 10 bits, 10 UI on the serial link.

2. What is the depth/size of the DP159 FIFOs ?

3. Could you please provide some info the DP159 “TMDS lane deskew” operation:
a. Description/details of the operation of the “TMDS lane deskew” function that the DP159 datasheet mentions ?
b. How the TMDS lane deskew function operate when in X-mode ?

Regards,
Kris

Kris

Are you seeing any functional issue with DP159 that you are trying to debug?

A lot of these questions involved the detail of DP159 design which I can't share. But TMDS lane deskew function is not supported when DP159 is in x-mode. DP150 does not perform lane to lane deskew in x-mode.

Thanks
David

Hi David, 

Yes we are observing DP159 output lane-to-lane skew that violates the DisplayPort spec. Please refer to the DP159 lane-to-lane skew captures in the attached document "DP159_Captures_v0.pdf". The input of the DP159 is consistent at approximately 2 symbols skew, but the DP159 output skew various between zero skew, leading skew, and lagging skew on successive DP159 power cycle and reconfiguration. 

Regards,
KT

DP159_Captures_v0.pdf

KT

What you saw is expected as DP159 skew compensation is disabled in the DP retimer mode, and sometimes the skew will exceed the DP spec. But the endpoint at the output of DP159 will have enough margin to de-skew this inter-pair skew.

Thanks
David

Hi David, 

An explanation from our digital design team of why the DP159 output skew violation/variation is a problem:

"Hi David,

I do not agree with your statement that “the endpoint at the output of DP159 will have enough margin to de-skew this inter-pair skew”. If a host is using TPS2 for equalization the maximum number of inter-lane symbol skew that can be de-skewed is 2 +/- 4, so anything from -2 to 6 symbols of skew. 2 is the number of symbols inserted by the host (see input captures) and is a known skew. The maximum de-skew possible relative to that is half the number of test pattern symbols less 1. For TPS3 this means a maximum de-skew of 16 symbols and for TPS2 this is 4 symbols.

Looking at the provided captures you can see that:

• Capture #4 has a skew of -4 symbols violating the -2 to 6 symbol skew range that TPS2 can de-skew
• Capture #5 has a skew of 7 symbols violating the -2 to 6 symbol skew range that TPS2 can de-skew

As soon as the inter-lane skew exceeds the -2 to 6 symbol range the lane alignment logic will result in an incorrect lane alignment after de-skew when using TPS2. This means incorrect video is displayed once link training is done.

How can we prevent the DP159 from adding or removing multiple symbols of skew?

Regards,
RVS"

Handle through direct email.

Thanks
David

Issue still not resolved.