Original question:
Now we also have a project disigned with LMH1983 and xilinx ultrascale fpga for 12G-SDI input and output.
Because the performance of LMH1983 (PLL2 & PLL3) does not meet the Kintex ultrascale FPGA specifications, so i also plan to add LMK03328 for jitter clean.
I want to make sure than can i use a single chip LMK03328 for both PLL2 and PLL3 output clocks simultaneously。
Thanks a lot!
Yes, LMK03328 can generate both 148.xx MHz clock simultaneously, but I would highly recommend to use the 27 MHz output clock (from PLL1 of LMH1983) as the reference clock to the LMK03328, because the 27 MHz output has lower jitter compared to 148.xx MHz outputs (from PLL2/3). Having the lower jitter 27 MHz reference will ensure LMK03328 has low jitter on its output clocks. LMK03328 can precisely generate 148.5 MHz (integer PLL mode) and 148.5 MHz/1.001 (fractional PLL mode) from the 27 MHz reference, so that these clocks are synchronous to the incoming Hsync reference of the LMH1983.
We have already implemented this proposed LMH1983+LMK03328 clock tree in an FPGA reference design offered by an external vendor:
FPGA HVF --> LMH1983 --> (27 MHz LVDS) --> LMK03328 --> 148.5 MHz or 148.5 MHz/1.001 (or 2x clock rate) --> FPGA SerDes
For reference, I am attaching an example LMK03328 config file (.tcs) that can be loaded into the TICS Pro EVM programming GUI. This config has already been evaluated to work with the LMH1983+LMK03328 architecture described above. Using TICS Pro, you can make changes to the configuration, then export/dump the register settings to a hex file so your FPGA can program the device.
LMK03328_PRIREF=27M_OUT2=148.35M(PLL2)_OUT4=148.5M(PLL1)_AC-LVDS.tcs
Hope this helps.
Alan
