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XIO3130: Power-up sequence

Guru 15520 points
Part Number: XIO3130
Other Parts Discussed in Thread: XIO2001

Hi,

I have questions about power-up sequence of XIO3130.

My customer are using XIO3130 and having some issue.
They are using EEPROM option of XIO3130 and enable that feature.
But when powering up the system, sometimes there are no active signal on SCL lines.
So, XIO3130 doesn't load the data from EEPROM.

A similar issue is posted to the following E2E.
In the following E2E, it seems the power-up sequence written in XIO3130 datasheet is incorrect.
And it seems we should follow the sequence written in XIO2001 datasheet.
This E2E are posted about 6 month ago but latest XIO3130 datasheet haven't updated yet,
so I'm quite confusing either I should follow the XI2001 datasheet or not.
e2e.ti.com/.../699987

Should I follow the power-up sequence of XIO2001 also in XIO3130?
I pasted the power-up sequence of each device in attached file, so please take a look.XIO2001_XIO3130 Power-Up Sequence.pdf
The difference are that GRST are not included in the power-up sequence of XIO3130.

If GRST need to be included in the sequence, when should it be de-asserted?
Is it just after all power stabled?
Or should it be de-asserted a few [ms] after all power supply stabled?

best regards,
g.f.

  • g.f.,

    XIO3130 GRST pin serves the purpose of latching the default values of internal registers as well as initializing (or re-initializing) other digital blocks. The XIO3130 power up sequence is not incorrect as GRST can be used to reset digital blocks at any time (asynchronous) during normal and Vaux power states. Please see "Table 3-5. Switch Reset Options" in the GRST row.

    If the XIO3130 power up sequence is followed the EEPROM interface will not initialize until GRST is de-asserted. In addition following a power up sequence similar to XIO2001 can also be valid for XIO3130 in this sense as the SCL pull up should be detected after PERST is de-asserted since is this case GRST is de-asserted right after power is stable. See section "3.4.1 Serial Bus Interface Implementation" in datasheet for more explanation.
  • Hi Malik,

    Thank you for the reply.

    I understood that XIO3130 power-up sequence written in XIO3130 datasheet is correct.
    So, the information from other E2E which I attached previously was mistaken, right?

    My customer are following the power-up sequence of XIO3130 right now,
    but sometimes it seems that XIO3130 doesn't drive the I2C SCL line and there are no active signal on I2C SCL line
    when starting up the XIO3130 as I mentioned above.

    I2C SCL and SDA lines are pulled up to 3.3V in there board.
    They checked each power lines and it seems all power are stable.

    We want to fix this issue, but don't know what to check next.
    Could you please advise us what should we do next?

    best regards,
    g.f.
  • g.f.,

    The information in that E2E thread was specific to that customer. What is the resistance of the pull-up resistors on the board? What EEPROM are you using in this application? I would be sure to use a high impedance probes when looking at the SCL and SDA lines with an oscilloscope.

  • Hi Malik,

    Thank you for the reply.

    This issue is happening at my customer,
    so that I need to ask them about the value of pullup resistor and EEPROM which they are using.
    Could you please wait for a while?

    By the way, they could see the activity of SCL and SDA when the XIO3130 working properly.
    So, I guess the probe of oscilloscope isn't the problem.

    best regards,
    g.f.
  • g.f.,

    I will be waiting for your reply. Could you also ask for scope captures of their power up sequence?

  • g.f.,

    Is there any more support needed for this issue? If so please reply with any relevant details so that I can further assist you. For now I will be marking this thread as "TI Thinks Resolved". If you have resolved your issue, please post the solution to the original problem/post for others with similar issues.
  • Hi Malik,

    I'm sorry for keeping you waiting.
    It's not resolved yet. I'm requesting scope capture to my customer, but I haven't got it yet and no response so far.
    I will be back as soon as I get reply from my customer.

    best regards,
    g.f.
  • g.f,

    Any update?
  • Hi Malik,

    I'm sorry for the delay.

    I have some updates.

    1. I got signal waveform from my customer. Please take a look at attached file.

    XIO3130 PWR_CLK_I2C_signal.pdf
    2. GRST is pulled-up to 3.3V externally.
    3. GRST and PERST of XIO3130 are connected to same reset signal.
       This reset signal is also used for resetting other CPU.
    4. I2C SCL and SDA are pulled-up to 3.3V via 4.7kohm resistor.

    There was no power supply rise waveform of power-on sequence,
    so that I'm requesting again.

    best regards,
    g.f.

  • Hi Malik,

    I received power-supply rise waveform of power-on sequence from my customer.
    Please take a look at the attached file.

    And I want to know that asserting/de-asserting GRST and PERST in same time
    are allowed or not for this device XIO3130.

    best regards,
    g.f.

    XIO3130_Waveform(Power-up Sequence).pdf

  • g.f.,

    It seems there is a small glitch in the PERST/GRST signal. Could the PERST/GRST be controlled externally such that this glitch is not present to see if the problem persists? The high voltage of this glitch appears to be higher than the specified low voltage for PERST/GRST. This may cause the part start the internal state machine before REFCLK is registered as valid. 

    Also it is valid for PERST and GRST to be tied together. 

  • Hi Malik,

    Thank you for pointing out the problem.
    I told my customer to reduce this glitch completely then check either the issue will be solve or not.
    As soon as I get the feedback I will share with you.

    best regards,
    g.f.
  • Hi Malik,

    I had a reply from my customer.

    They told me that reducing this glitch is unpossible.
    Because after powering on the board, it takes a few msec to setup the PIC microcontroller
    and then the RESET will be asserted for specified time.

    The level of glitch in PERST/GRST signal is 0.4V and
    this is under the range of XIO3130 specification.
    From datasheet, VIL of input pin is 0.3*VDD33 = 0.99V.

    And here are new information from the customer:
    this issue occurs not only just after power-on, but also it occurs when
    starting up from manual RESET. In such case, there no glitch in PERST/GRST.

    Are there anything else to check?

    best regards,
    g.f.
  • Hi g.f.

    Is this an intermittent issue? How often does the failure happen in their system? Do they have multiple systems that all have the same failure?

    Regards,
    I.K.
  • Hi I.K.,

    Thank you for the reply.

    The mass production have been started about 3 years ago,
    and they already released about 400 boards.

    The issue have never been occur until now,
    but the issue are occuring in 3 of 100 boards now .

    The issue will occur once every five times(20%) of powering on the XIO3130.
    And they told us this issue occur not only at power-on phase
    but also it sometimes occurs when it start running from manual reset.

    best regards,
    g.f.
  • Hi g.f.

    Has there been any changes in their system (schematic, hardware, etc.) up until now? It's strange how they have never previously seen the issue after having been in production for so long.

    Also, do their previous boards also have the glitch on PERST/GRST? Are there any differences in the waveforms between good boards and boards that show the issue?

    Regards,
    I.K.
  • Hi I.K.

    Thank you for the reply.

    They didn't change schematic, hardware, etc. There are no changes.
    That is why we are confusing.
    Do you think it's device(XIO3130) defects?

    >Also, do their previous boards also have the glitch on PERST/GRST?
    >Are there any differences in the waveforms between good boards and boards that show the issue?

    Although it may be at the begining of the next year(1/7), I'm asking to the customer now.
    So, please wait for awhile.

    best regards,
    g.f.
  • Hi g.f.

    If there really have been no changes then yes it is possible it could be a quality issue. Before we go down that route though we should eliminate all other possibilities by examining the differences in performance between their old system and their current system. Let's start by checking if the glitch is also present in their old system and any other differences in the waveforms.

    Regards,
    I.K.
  • Hi g.f.

    In addition, please also have them perform a swap test: put a failing unit on one of their old boards to see if it still fails, and take a good unit off of an old board and put it on one of the newer failing boards to see if it passes or fails. This will help to determine whether or not it's an issue with the unit itself.

    Regards,
    I.k.
  • Hi I.K.

    A Happy New year!
    Thank you for the reply.

    I got a reply from my customer about the following question:
    >Also, do their previous boards also have the glitch on PERST/GRST?
    >Are there any differences in the waveforms between good boards and boards that show the issue?

    Their previous boards also have the glitch on the PERST/GRST.
    The only differences in the waveforms between good boards and the boards that show the issue is
    I2C waveforms either operates properly or not.

    And I got an additional information.
    They producted 50 new boards in December,2018 but there are no issue of XIO3130.

    I don't know they can do the swap test but I will ask to the customer.
    Please wait for a while.

    best regards,
    g.f.
  • g.f.,

    Any update on this?
  • Hi Malik,

    I'm sorry about the delayed response from me.
    I asked to the customer about the swap test, but they said that doing test is unpossible.
    Because they don't have the board at their hand(It's at their end customer) and
    they don't want to taking off the XIO3130 from the board.

    I'm telling to my customer that the swap test is needed to decide if it is XIO3130 or board issue or not,
    and also telling them that if the test is unpossible it is hard to support in such a case.
    So, could you please wait for awhile?

    best regards,
    g.f.
  • g.f.,

    I will wait for your reply. I will continue to investigate and let you know, in this thread, if there is any other debug steps the customer can take. 

  • g.f.,

    Is there any more support needed for this issue? If so please reply with any relevant details so that I can further assist you. For now I will be marking this thread as "TI Thinks Resolved". If you have resolved your issue, please post the solution to the original problem/post for others with similar issues.
  • Hi Malik,

    Thank you for the reply and sorry for the delay.

    I hadn't heard from the customer that this issue have been solved so far.
    We are asking to the customer but we haven't get the response and additional infromation
    from the customer this few weeks

    As I mention above post, they can't do the swap test.
    Also, similar problems have not occurred with 500 units manufactured in December, 2018.
    So, may be they given up investigating the cause.

    We will keep following up the customer but I don't know when they will reply to us.
    So, I guess I should close this thread.
    I apreciated your support. Thank you so much.

    best regards,
    g.f.
  • g.f.,

    I understand g.f., thank you for your hard work. I will mark this thread as TI thinks resolved.