LMH1982: No lock indication of SD_LOCK

Did you try the suggestions in the other thread you linked, such as maximizing ICP1 to compensate for any leakage current due to VCXO input resistance and/or loop filter path, or maximizing the LOCK_CTRL value to relax the phase lock threshold?  It the VCXO input resistance is low enough to contribute enough leakage to introduce a phase error at the PLL1 PFD inputs, you may need to add an op-amp with high input impedance (like LMP7711) to buffer between the loop filter voltage to and VCXO input.

Alan