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Original question:

TUSB8041: Windows Software to Configure USB Hub

TUSB8041: TUSB4041I EEPROM programming tool

Balazs Soregi
Prodigy 105 points
Part Number: TUSB8041
Other Parts Discussed in Thread: TUSB4041I

Dear TI Team,

I design a board with TUSB4041I hub ICs. I could download TUSB80xx EEPROM programmer only. Is it an applicable programming tool for TUSB4041I too? If not, please send me a link for the right tool.

One of community post mentioned, that TI USB hub ICs can be forced programming mode again so that to edit EEPROM content by pulling to logic Hi level both DM and DP signal pins of any of their downstream ports. Does it work in case of TUSB4041I too?

Thank you in advance.

Best regards,

Balazs Soregi

  • 0
    TI__Guru 60870 points
    Hi Balazs,

    Yes, the same EEPROM programming tool works for all the TUSB80xx and TUSB40xx family of devices. We do not recommend using the method of pulling DP and DM high to force entry to programming mode since there is the possibility of damage to the device. It is possible to simply load the programming driver on the USB 2.0 instance of the hub in Device Manager to force the hub into programming mode.

    Regards,
    JMMN
  • 0 in reply to JMMN
    Prodigy 105 points

    Hi JMMN,

    Thank you for your reply. My project is at the beginning of PCB design. As soon as the prototype is ready, I will try it. I still have problems related to this project, so let me describe it in a bit more detailed way and let me ask you some more questions.

    The project:

    - Self powered USB hub with 3 pcs TUSB4041I, one is connected to the host computer by its upstream port, its downstream ports 1 and 2 are connected to the 2nd and 3rd ones upstream ports, downstream ports 3 and 4 are connected a USB-UART and a USB-I2C converters.

    - The 2nd TUSB4041I should have individually switched VBUS signals at its downstream ports, the 3rd one should have ganged switching.

    - Battery charging is not necessary at all.

    - Eurocard 160x100 mm physical size.

    My problems:

    1. Some of device pins have pull down or pull up resistors with tipical values of 13.2 kOhm and maximal values of 22 kOhm. I can see in a lot of schematics, that external resistors are added (4.7 kOhm, 10 kOhm, etc.) in the same direction as the inner resistor. Can the inner resistors ensure enough strong logic low or high levels for safe and stable operation? What is your suggestion in case of pins sampled after RESET OVERCURnz pins. I have routing routing difficulties in the mentioned board size, so each component which can be left out makes my jobis a bit easier.

    2. The datasheet suggests (Figure 33, page 34) 100 nF filter capacitors for each VDD and VDD33 pins plus one 10 uF for both power supplies. The evaluation board uses 1 nF, 10 nF and 100 nF capacitors connected parallel for each power supply pins. No question for me, that the last one is better solution, but I don't know how much is better. Do I really need 3 pcs of parallel filter capacitors for each pins?

    3. The input of VBUS signal resistor divider of the 1st hub is connected to the +5V of its upstream port connector. Where should I connect the inputs of VBUS resistor dividers of the 2nd and 3rd hubs?

    4. I need to change the polarity of some downstream ports of DM and DP signals by EEPROM configuration so that I can avoid layer change for any of them. How will EEPROM programming work in case of concatenated hubs? If I need to reprogram any of them and Windows causes some not waited surprise, could you suggest safe value of pulling up resistors for DM and DP signals to force the hubs to enter into programming mode?

    5. 3 pcs of hub ICs with 24 MHz clocks and 2 pcs of other ICs with 12 MHz clocks. I must decide whether I use 5 pcs of quartz crystals or clock distribution with one quartz oscillator and a D-type flip-flop 1:2 divider followed by clock buffer ICs. What is your suggestion?

    6. The 3rd hub will use ganged VBUS switching, which means the device has 3 pcs of not used PWRCTL and OVERCURz pins. Is there any method to use them as GPIO pins?

    7. The evaluation board uses AT24C04 EEPROM for I2C configuration, which is internally organized in a 512x8 bit matrices. The memory map of TUSB4041I shows byte addresses up to FFh only, which means a 256 byte EEPROM should be enough. Is there any special reason to use a bigger one?

    Excuse me because of a lot of questions, but I couldn't find answers anywhere to them.

    Thank you in advance.

    Best regards,

    Balazs Soregi

  • 0 in reply to Balazs Soregi
    TI__Guru 60870 points
    Answers in-line below:

    1. Some of device pins have pull down or pull up resistors with tipical values of 13.2 kOhm and maximal values of 22 kOhm. I can see in a lot of schematics, that external resistors are added (4.7 kOhm, 10 kOhm, etc.) in the same direction as the inner resistor. Can the inner resistors ensure enough strong logic low or high levels for safe and stable operation? What is your suggestion in case of pins sampled after RESET OVERCURnz pins. I have routing routing difficulties in the mentioned board size, so each component which can be left out makes my jobis a bit easier.

    [JMMN] If the internal pull-up / pull-down on a configuration pin matches your preferred setting, there is no need to use an additional external pull-up / pull-down resistor. External pull-ups on OVERCURnz are not required, we typically put these in reference designs in case an application is very noisy since even a spurious overcurrent event will stop the hub from working.

    2. The datasheet suggests (Figure 33, page 34) 100 nF filter capacitors for each VDD and VDD33 pins plus one 10 uF for both power supplies. The evaluation board uses 1 nF, 10 nF and 100 nF capacitors connected parallel for each power supply pins. No question for me, that the last one is better solution, but I don't know how much is better. Do I really need 3 pcs of parallel filter capacitors for each pins?

    [JMMN] Reference designs / EVM s usually have more filter capacitors and bulk capacitors then is required. I would recommend at least one filter cap per power pin if possible.

    3. The input of VBUS signal resistor divider of the 1st hub is connected to the +5V of its upstream port connector. Where should I connect the inputs of VBUS resistor dividers of the 2nd and 3rd hubs?

    [JMMN] There are two possible solutions, one is to connect the VBUS of the 2nd tier hubs to the same VBUS as the upstream port. The other is to use the PWRCTL outputs of the 1st tier hub to drive VBUS to the downstream hubs.

    4. I need to change the polarity of some downstream ports of DM and DP signals by EEPROM configuration so that I can avoid layer change for any of them. How will EEPROM programming work in case of concatenated hubs? If I need to reprogram any of them and Windows causes some not waited surprise, could you suggest safe value of pulling up resistors for DM and DP signals to force the hubs to enter into programming mode?

    [JMMN] Using the USB based EEPROM programming tool is going to be difficult in a tiered hub system, once the first hub is programmed, you will not be able to tell which 2nd tier hub is being programmed first. If you force the hub into programming mode using the method of pulling DP and DM high, make sure they are not pulled higher than 3.3V and that the voltage source is current limited. Also, if you are using EEPROM, you don't need to worry about the configuration pin settings - the EEPROM settings will override the pin settings.

    5. 3 pcs of hub ICs with 24 MHz clocks and 2 pcs of other ICs with 12 MHz clocks. I must decide whether I use 5 pcs of quartz crystals or clock distribution with one quartz oscillator and a D-type flip-flop 1:2 divider followed by clock buffer ICs. What is your suggestion?

    [JMMN] Either will work, just make sure if a oscillator is used it is 1.8V and the routing is as clean as possible.

    6. The 3rd hub will use ganged VBUS switching, which means the device has 3 pcs of not used PWRCTL and OVERCURz pins. Is there any method to use them as GPIO pins?

    [JMMN] No, even if they are not used in the GANGED configuration,they are still functionally PWRCTL / OVERCUR pins.

    7. The evaluation board uses AT24C04 EEPROM for I2C configuration, which is internally organized in a 512x8 bit matrices. The memory map of TUSB4041I shows byte addresses up to FFh only, which means a 256 byte EEPROM should be enough. Is there any special reason to use a bigger one?

    [JMMN] As long as the entire register map can fit in the EEPROM, I don't see why a AT24C02 would not work.

    Regards,
    JMMN
  • 0 in reply to JMMN
    Prodigy 105 points

    Hi JMMN,

    Thank you very much for your deatailed answer.

    Best regards,

    Balazs Soregi