Part Number: TLK10034
Hello,
We are using TLK10034 PHY connected to an external switch the block diagram of the same is attached with the mail.
Please find the 10G Base-KR data path block diagram.
We are using Jaguar-2 VSC7468 L2 Switch.
Following is our observation.
ON the PHY Side:
1. After the configuration of the Link Partner Device(Jaguar2 Switch< Microsemi>), We see the following changes in the registers if the TLK device.
a) Device Address : 0x1E Register Address : 0x0x000F
In the register, the Value toggles between, 0x3003/0x1003/0x1803
b) Device Address : 0x07 Register Address : 0x0x0001
In the register above, the value toggles between 0x88/0xCD/0x8D
c) Device Address : 0x01 Register Address : 0x0x0097
In the register above, the value toggles between 0x4/0x6/0xC
d) Device Address : 0x07 Register Address : 0x0x0030
In the register above, the value toggles between 0x0011/0x0001
Our observation is AN_COMPLETE bit is never set during the course of our observation.
ON the SWITCH Side(Link Partner):
I have observed that in the Switch Training register DME Violation Bit is set and Loss of training frames lost bit is set.
Also, I have seen that 10G-KR negotiation bit is toggling in Switch also. 
