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DS90UB928Q-Q1: Question of invalid I2C transaction

Part Number: DS90UB928Q-Q1

Hi team,

For the I2C communication between host <-> DS90UB927-Q1 <-> DS90UB928Q1 <-> slave device, can you answer the followings?

-. When there is no Stop signal (ACK or NACK) after Start and Data while communicating between Host IC, DS90UB928-Q1 and slave device via I2C, can you explain the behavior of DS90UB928-Q1?

-. For I2C Bus Watchdog Timer (0x06), is it working for the communication of DS90UB928-Q1 and slave device?

   : Bit 0(I2C Bus Timer Disable) = "0" for enable and "1" for disble  Is it correct?

Thanks,

Sam Lee