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DS125DF410: CDR Setting

Part Number: DS125DF410
Other Parts Discussed in Thread: LMH1226

Hi, team.

I have a question about DS125DF410 CDR regsiter setting.

I have the problem that a video signal via DS125DF410 does not output .

But when CDR was bypassed, a video signal could output.

I think CDR settings is not enough.I want you to teach a method of analysis.

Now, DS125DF410 register is set as follows.

DataRate Setting(5.94Gbps only)

ADDR   DATA

0x2F     0xB6

0x60    0x66

0x61    0xBB

0x62    0x66

0x63    0XBB

0x64    0xFF

CTLE setting(15dB fixing)

0x31  0x00

0x3A  0x52

0x03  0x52

Best regards.

  • Greetings,
    Please use the following register settings to enable lock to this data rate:
    0x2F = 0x26
    0x60 = 0xB3
    0x61 = 0x9D
    0x62 = 0xB3
    0x63 = 0x9D
    0x64 = 0xFF
    Please let us know.
    Regards,,nasser
  • I try your data. but a video signal was not output.

    By the way,when a video signal was not output that I showed,  a value of Retimer's Addr 0x02 was 0x00.

    Do you know what it is from this value?

    Regard.

  • Greetings,

    Normally when bits 4 & 3 are set this indicates device is locked. Even if these two bits are not set, I was expecting other bits to get set.

    Please note LMH1226 device automatically locks to this data rate - and 10GbE as well. Please let me know your application for using DS125DF410 to lock to 5.94Gbps data rate. There could be other settings that are needed. If you like you can send me email at Nasser.mohammadi 

    Regards,,nasser

  • Hi,team.

    An answer becomes slow,and I am sorry.
    The detailes thing cannot say, but the application uses the high speed signal using the IP of FPGA.
  • Hi,team.

    I inform it of the setting value which i set some other day
    because setting value of CTLE which I showed had an omission of mention.

    ■Data rate setting
    REG DATA
    0x2F 0xB6
    0x60 0x66
    0x61 0xBB
    0x62 0x66
    0x63 0xBB
    0x64 0xFF

    ■CTLE setting(15dB fixing)
    REG Data
    0x31 0x00
    0x03 0x52
    0x2D 0x88
    0x3A 0x52
    0x40 0x52

    The setting of data rate is calculated by a calculation methed listed in datasheet.
    Retimer works by this setting normally under the normal temparature environment(abut 25~28℃).
    But, specific channel of Retimer dose not lock under low temperature enviroment(-5℃).
    Therefore FPGA of the latter half can not recieve a signal.

    When this problem was occured, FPGA was not able to recieve a signal was able to recieve a signal
    when I switched to setting to bypass CDR.

    ■CDR Bypass mode
    REG Data
    0x09 0x20
    0x1E 0x09

    When CDR was validated, REG 0x02 Data 0x00.
    When CDR was bypassed, REG 0x02 Data 0xDC.

    From these results, I think that CDR dose not function.
    What should I do to functionalize CDR effectively?

    When there is not the method that CDR functionalizes, I want to adopt a CDR bypass mode.

    Is there not the problem by this how to use?

    Best regards.
  • Hi Megata,

    DS125DF410 temperature lock range is 100degC and DS125DF410 operating temperature range is -40 to +85degC.
    1). When measuring -5degC, at what point are you making this measurement?
    2). There is a way you can enable the device to go into raw mode when device is not locked. Please below note register settings for this operation:
    Reg 0x09[5]=1'b1 //set bit 5 of reg 0x09
    Reg 0x1E[7:5]=1'b000 //set bits 7 through 5 of reg 0x1E to 0000

    Regards,,nasser
  • Hi, nasser.

    > 1). When measuring -5degC, at what point are you making this measurement?

    A trial product is put in a constant temparature tank.

    I set the temparature setting of the constant temparature tank to -5 degC.

    >2). There is a way you can enable the device to go into raw mode when device is not locked. Please below note register settings for this operation:
    >Reg 0x09[5]=1'b1 //set bit 5 of reg 0x09
    >Reg 0x1E[7:5]=1'b000 //set bits 7 through 5 of reg 0x1E to 0000

    The setting mentioned above has already set it.

    Dose the raw mode come by a movement guarantee as DS125DF410?

    Had it not been for setting to be able to lock, I want to operate it with raw mode.

    Best regard.

  • Greetings,

    1). I am trying to understand the temperature DS125DF410 device is exposed to. Your temperature tank could be at -5degC but how about DS125DF410 device. Is this also at -5degC or lower? DS125DF410 is rated at -85degC.

    2).  You said: Does the raw mode come by a movement guaranteed by DS125DF410".

    Here I am assuming you mean does DS125DF410 go into raw mode if there is no lock and the answer is yes. DS125DF410 - using register settings that I noted earlier - will go into raw mode if device is not locked.

    Regards,,,nasser

  • Hi, nasser.

    > 1). I am trying to understand the temperature DS125DF410 device is exposed to. Your temperature tank could be at -5degC but
    > how about DS125DF410 device. Is this also at -5degC or lower? DS125DF410 is rated at -85degC.

    Because I put a board in a tank, probably I think that the temparature of DS125DF410 device reach approximately -5 degC.
    -5 degC is temparature to evaluate of the products.

    > 2). You said: Does the raw mode come by a movement guaranteed by DS125DF410".
    > Here I am assuming you mean does DS125DF410 go into raw mode if there is no lock and the answer is yes. DS125DF410 -
    > using register settings that I noted earlier - will go into raw mode if device is not locked

    I examine it in various ways and use raw mode if there is not at method to lock.

    By the way, data of reg 0x02 was 0xDC at raw mode.
    Though CDR is not used, why dose data of reg 0x02 become 0xDC?

    Best regard.
  • Greetings,

    This is ok. When in raw mode, there are two signal paths: One going to a mux that drives the 100-ohm output driver. The second signal path takes this signal to CDR block which is monitoring incoming signal. So it is possible to operate in raw mode and CDR reg 0x02 show 0xDC value.

    Regards,,nasser
  • Hi,Nasser.

    Is MUX which you say a part of the red frame of figure which I attached?

    Regard.

     MUX_of_Block_Diagram.pptx

  • Greetings,
    Yes MUX you have pointed in the presentation that you just sent me is a the same mux that I had mentioned earlier.

    Please use the same settings that you have mentioned in your email. Additionally set the following register settings as well:
    a). Channel reg 0x18[6:4] = 3’b001
    b). Channel reg 0x09[2] = 1’b1
    This forces divide by two settings for the VCO.
    Regards,,nasser
  • Hi.Nasser.

    When I watched Block diagram which have pointed, 

    only pattern generator and the signal which is output from CDR is input to the MUX.

    The output from CTLE dose not seem to be connected directly?

    Actually, is the output from CTLE connected to MUX directly,too?

    Regard.

  • Hi Maegata,
    Please note figure 3 of the DS125DF410 data sheet. There is a path from CTLE to the mux at the output of the CDR.
    Regards,,nasser
  • It is guessed by your comment so that there MUX to change the path which does not go by way of CDR and tha path going way of CDR in CDR/Retimer.

    I think that it become like the document which I attached.

    Dose my recognition match yuor recognition?

    MUX_of_Block_Diagram2.pptx 

  • Hi Maegata,
    Your understanding is correct.
    Regards,,nasser
  • Hi, Nasser.

    when the path which dose not go by way of CDR was used, data of Reg 0x02 was 0xDC(Values of Reg 0x02 bit 4:3 ware 1)

    Though the path going by way of CDR is not used, why ware values of Reg0x02 bit4:3 1 (CDR Lock) ?

    Regard.

  • Hi Maegata,
    This is expected. Output of CTLE goes to two places: One to CDR and another to the mux that bypasses the CDR. While signal bypasses the CDR, at the same time this signal goes to the CDR block as well - this is why you are seeing reg 0x02[4:3]=2'b11.
    Regards,,nasser
  • Hi, Nasser.

    Thank you for a replay.

    I understand that reg 0x02[4:3]=2'b11 when  a signal dose not go by way of CDR.

    Just I have a quesion.

    If a signal goes by way of CDR at same setting as raw mode(setting other than raw mode setting),

    reg 0x02 = 0x00 in my retimer. Of course 0x02[4:3] =2'b00.

    I want to know why it become reg 0x02 = 0x00(0x02[4:3] =2'b00).

    Please tell me if there are points to be confirmed.

    Regard.

  • Hi Maegata,

    Please note section 7.5.10 of the DS125DF410 data sheet. Reg 0x09[5] and reg 0x1E[7:5] control this mux's output.If device is not locked output will be muted.

    Regards,,nasser

  • Hi,Nasser.

    When switching from the path which dose not going by way of CDR to the path going by way of CDR, CDR is not locked.  

    The same signal is input to CDR as when bypassing CDR, but why is CDR is not locked?

    Regard.

  • Hi Maegata,

    If I understand you correctly, you put DS125DF410 in bypass mode and you observe device is locked. Then you change mux settings to enable retimer path then you notice CDR is not locked. If this understanding is correct, please note the following:
    1). First of all, please make sure you read lock indication to be certain device is locked.
    2). When device is in bypass and CDR is locked, please change your CTLE settings to make sure you have good HEO/VEO eye opening margin. Suggestion is to optimize your CTLE settings so you would get HEO about 0.7UI and VEO in order of at least 250mV or higher.
    In my case and at 5.94Gbps, when I switch from bypass to retimed mode device stays lock. Please note getting good HEO/VEO number(VEO more than 300mV and HEO about 0.75UI).
    3). When you switch from bypass to retimed mode and CDR is not locked, please do the followings: Put device in adapt mode 1 or adapt mode 2 and then reset CDR. Does this enable device to lock?

    Regards,,nasser
  • Hi,Nasser.


     >If I understand you correctly, you put DS125DF410 in bypass mode and you observe device is locked. Then you change mux settings to enable retimer path then you notice CDR is not locked.

    >If this understanding is correct, please note the following:

    Your understanding is correct.

    >1). First of all, please make sure you read lock indication to be certain device is locked.

    When I switch from CDR mode to bypass mode, The data of reg 0x02 switches from 0x00 to 0xDC.

    >2). When device is in bypass and CDR is locked, please change your CTLE settings to make sure you have good HEO/VEO eye opening margin.

    >Suggestion is to optimize your CTLE settings so you would get HEO about 0.7UI and VEO in order of at least 250mV or higher.

    >In my case and at 5.94Gbps, when I switch from bypass to retimed mode device stays lock. Please note getting good HEO/VEO number(VEO more than 300mV and HEO about 0.75UI).

    The value of HEO and VEO at raw mode are as follows.

                ch0                     ch1                       ch2                       ch3    HEX(DEC)

    HEO   0x20(0.514UI)     0x23(0.5521UI)    0x26(0.5938UI)    0x22(0.5313UI)

    VEO   0x8A(431.3m      0x7C(390.6mV)   0x8F(446.9mV)     0x88(428.1mV)

    >3). When you switch from bypass to retimed mode and CDR is not locked, please do the followings:

    >Put device in adapt mode 1 or adapt mode 2 and then reset CDR. Does this enable device to lock?
     

    I try adapt mode1 and adapt mode 2.
    Two results are as follows.
    1) adapt1
                      ch0     ch1      ch2      ch3
     reg0x02   0xDC   0xDC   0xDC  0xDC
     reg0x03   0x00    0x99    0xA0   0x69
    Because the equalization amount of ch0 is too lower than other ch,
    FPGA can not recieve a signal of ch0.
    2) adapt2
                      ch0     ch1      ch2      ch3
     reg0x02   0xDC   0xDC   0xDC  0xDC
     reg0x03   0x00    0x57    0x5D   0x99
    same result as adapt1
    Because the equalization amount of ch0 is too lower than other ch,
    FPGA can not recieve a signal of ch0.

    Regerd.

  • Hi Maegata-San,
    Discussed this with Shidara-San and we have a test/experiment plan. He will be in contact with you to discuss these in more details.
    Regards,,nasser
  • Hi, Nesser.

    I understand.Thank you for your help

  • Hi Maegata,
    Based on discussions with Shidara-San, you are now working with cable vendor on this issue. I am closing this E2E thread. Please let Shidara-San or I know if there is an update.
    Regards,,nasser
  • Hi Nasser

    I sent update information via e-mail to Shidara-san this morning.

    Please discuss with Shidara-san.

    Regard.