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Original question:

TL16C2550 td8 timing

TL16C2550: td8 timing

rabe_ksks
Prodigy 50 points
Part Number: TL16C2550
Other Parts Discussed in Thread: TMS320VC5507,

Hi team,

I read the original question, but I didn't understand.

Therefore, td8 means that A2-A0 should be determined 7ns before or more a falling edge of /IOR, right?

Regards,

  • 0
    TI__Guru 73271 points
    Hey Rabe,

    From my experience with using our UART devices, the timing does seem to be based on the IOW/IOR falling edge. You should have the address pins AND CSx pin in their logic state (such as if you want to write to A channel then you want below 50% of Vcc) before IOW/IOR is driven low. So yes, if you are operating at 3.3V or higher then you want to have a 7 ns delay between when the address pins and chip select go low and then the IOW/IOR pin goes low.

    Thanks,
    -Bobby
  • 0 in reply to BOBBY
    Prodigy 50 points
    Hi Bobby,

    Thanks to you.
    I resolved.

    I try UART on TMS320VC5507 with EMIF via TL16C2550.
    I worried, because address pins are driven the same as or later than /CE pin on setup cycle.

    Regards,
    -Rabe