my design as follows ：DS90UB954+TX2；
During the hardware test，I want to test the side of ds90ub954,so I use the internal pattern generation featureuse
The config of the ds90ub954 is according to the demo,as follows:
# Python script CSI_patgen_RAW12_1280x720p30
# Version 0.91
# board.WriteReg(0x32, 0x01)
board.WriteReg(0x33, 0x03)
board.WriteReg(0xB0, 0x02) # IA_AUTO_INC=1
board.WriteReg(0xB1, 0x01) # PGEN_CTL
board.WriteReg(0xB2, 0x01) # PGEN_ENABLE=1
board.WriteReg(0xB2, 0x33) # PGEN_CFG
board.WriteReg(0xB2, 0x2C) # PGEN_CSI_DI
board.WriteReg(0xB2, 0x07) # PGEN_LINE_SIZE1
board.WriteReg(0xB2, 0x80) # PGEN_LINE_SIZE0
board.WriteReg(0xB2, 0x00) # PGEN_BAR_SIZE1
board.WriteReg(0xB2, 0xF0) # PGEN_BAR_SIZE0
board.WriteReg(0xB2, 0x02) # PGEN_ACT_LPF1
board.WriteReg(0xB2, 0xD0) # PGEN_ACT_LPF0
board.WriteReg(0xB2, 0x03) # PGEN_TOT_LPF1
board.WriteReg(0xB2, 0x20) # PGEN_TOT_LPF0
board.WriteReg(0xB2, 0x10) # PGEN_LINE_PD1
board.WriteReg(0xB2, 0x47) # PGEN_LINE_PD0
board.WriteReg(0xB2, 0x0A) # PGEN_VBP
board.WriteReg(0xB2, 0x0A) # PGEN_VFP
board.WriteReg(0xB2, 0xAA) # PGEN_COLOR0
board.WriteReg(0xB2, 0x33) # PGEN_COLOR1
board.WriteReg(0xB2, 0xF0) # PGEN_COLOR2
board.WriteReg(0xB2, 0x7F) # PGEN_COLOR3
board.WriteReg(0xB2, 0x55) # PGEN_COLOR4
board.WriteReg(0xB2, 0xCC) # PGEN_COLOR5
board.WriteReg(0xB2, 0x0F) # PGEN_COLOR6
board.WriteReg(0xB2, 0x80) # PGEN_COLOR7
board.WriteReg(0xB2, 0x00) # PGEN_COLOR8
board.WriteReg(0xB2, 0x00) # PGEN_COLOR9
board.WriteReg(0xB2, 0x00) # PGEN_COLOR10
board.WriteReg(0xB2, 0x00) # PGEN_COLOR11
board.WriteReg(0xB2, 0x00) # PGEN_COLOR12
board.WriteReg(0xB2, 0x00) # PGEN_COLOR13
board.WriteReg(0xB2, 0x00) # PGEN_COLOR14
board.WriteReg(0xB2, 0x00) # Reserved
up_vs：the output vsync of ds90ub914
up_line_valid：the output hsync of ds90ub914
up_exposure：the output pass of ds90ub914
up_reset：the output lock of ds90ub914
up_dout：the output 8-bits data of ds90ub914
up_pixclk：the output pixclk of ds90ub914
burst_line：the line counts of a frame
During the test，I did not do any configrations of ds90ub913 and ds90ub914. Ds90ub914 configed as 12-bit low frequency（cmos output 320*240, which the pixclk is about 13MHZ,60fps）, through the signalwave, the sync and the control signals such as vsync,hsync,lock,pass,pixclk are all correct, but the image date is always 0x20 during the row time,and change to be 0x00 during the row blank time.
My questions are:
1, what reasons maybe cause the problem?
2, Should the registers of ds90ub913 and ds90ub914 be configured?（cmos will be configured by fpga, not through ds90ub913 and ds90ub914）
