DP83867IR: no link while using the KCU116 devboard

Part Number: DP83867IR

I am having trouble getting a link established.
The board I am using is the Xilinx KCU116 and the schematics are on pg 46 of the following:
https://www.xilinx.com/support/documentation/boards_and_kits/kcu116/ug1239-kcu116-eval-bd.pdf

The 'link-partner' in this case is a 5-port GigE Cisco switch (SLM2005)

My hardware setup is known good as I can get a link light by simply loading a xilinx pre-built fpga:
https://www.xilinx.com/member/forms/download/design-license.html?cid=8c4791a3-0d7d-458c-bc14-a83c19a2dbd8&filename=xtp460-kcu116-ipi-c-2018-3.pdf
The only problem is, I don't know what the fpga is doing in order to get a link established.  And I also don't have access to the PHY registers when this FPGA is loaded.

After I load my own FPGA I then set the PWR and RESET_N pins high and am able to read/write the PHY registers:
I set 0x00 to 0x1140 to enable auto-negatiation
I set 0xD3 to 0x4000 to enable the 625 MHz reference clock.
If I set 0x16 to 0xD008 the FPGA is able to receive (via SGMII) the generated packets.
I have made no attempt to transmit packets yet.

What am I not doing in order to get a link established?