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Original question:

SN65DP159: PLL LOCK_COMPLETE Bit Remains Stuck at b1

SN65DP159: May we know what is SN65DP159 4K@60Hz Register setting Value ?

Chen Bogey8
Mastermind 9990 points
Part Number: SN65DP159

Hi Sir 

  1. FHD output unstable.
  2. 4K@60Hz Register setting Value  

                                                                Bogey

  • 0
    TI__Guru**** 176991 points
    Bogey

    DP159 does not have a particular register setting value for a particular resolution. Can you please dump out both Page 0 and Page 1 of the DP159 register? Can you also please share your schematic and layout?

    Is DP159 stable with lower resolution?

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Mastermind 9990 points

    Hi David

    May we know how to dump the page 0 and 1 registers?

    And may we check as below questions with you?

    1. We setting the DP159 under register mode, so no any register value we need thru I2C setting into DP159?
    2. 50% DP159  can work on 1920x1080@60hz but some  time got random no display problem
    3. Pls see attached sch.

                                                                      BogeyDP159.pdf

     

  • 0 in reply to Chen Bogey8
    TI__Guru**** 176991 points
    Bogey

    1. I would leave TX_TERM_CTL pin floating so the termination can be automatically selected between HDMI1.4 and HDMI2.0 when DP159 is in pin strap mode. When in I2C mode, the termination has to be set appropriately depending on HDMI1.4 and 2.0.
    2. I don't see the thermal GND being defined in the schematic, do they have thermal GND connected?
    3. Why do they need PI3C3125, DP159 supports I2C over AUX, so I don't know why you need it
    4. Do they have pullup on HBV1A_SSCL_2 and HBV1A_SSDA_2?
    5. Do they have 2k pullup on SDA_SRC/SCL_SRC and SDA_SNK and SCL_SNK? They may need a I2C buffer for DDC capacitance isolation
    6. Is the HPD connection direct or go through DP159?

    Please refer to table 4 for I2C address, write 0x00 to register 0xFFh, and start to dump register from 0x00h to 0xFFh. Write 0x01 to register 0xFFh, and do another dump from 0x00h to 0xFFh.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Mastermind 9990 points

    Hi Sir

    we now have condition that now we total run 10 pcs board. and there 4 pcs board is alway smooth. 6 pcs will random no display.(there will normal output when we down throughput)

    Is SN65DP159 need power sequency or concern about power noise?

                                                                                                 Bogey

  • 0 in reply to Chen Bogey8
    TI__Guru**** 176991 points
    Bogey

    Please refer to Figure 22 of the DP159 data sheet for power sequence requirement. VCC/VDD needs to be ramped up first, then OE needs to transition from low to high for DP159 normal operation.

    Please also dump out register between passing and failing board so we can compare the difference.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Mastermind 9990 points

    Hi Sir

    The DP159 reg as attached. may you have suggestion?

  • 0 in reply to Chen Bogey8
    TI__Guru**** 176991 points
    Bogey

    Can you please send the schematic and layout? The register dump shows lane de-skew is not completed. What is the skew between each lane?

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    TI__Guru**** 176991 points
    Bogey

    Do you have an update to this thread or can we close this thread?

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Mastermind 9990 points

    Hi Sir

    Pls closed it, if there have issue, i will post new question.

                                                                     Bogey