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Original question:

TLK2711-SP: TLK2711A GTX_CLK floating

TLK2711-SP: TLK2711A

amnon pomerants
Intellectual 780 points
Part Number: TLK2711-SP

Hello

In my card the TLK2711A is connected to a Virtex4 FPGA.

To consume power at standby mode we turn off the TLK2711 Vdd and deactivate the FPGA by pulling down its ProgB pin (its HSWAPEN pin is at "0").

Point is that in such situation the FPGA deliver "1" over its all IO pins, thus the SerDes IO pins fills 2.5V where its Vcc=0.

This is an obvious violation of the "Absolute Max Rating" demanding that Vih < Vdd + 0.3

However, the FPGA "1" while at ProgB state (NOT loaded)  is actually delivered by its internal very weak pull up (200uA max at Vdd=2.5V)

Is such a low current can harm the powered off SerDes?

Can I disregard the above violation?

Can I continue with the above power down saving scenario?

Looking forward to hear from you.

Thanks

Amnon

  • 0
    Intellectual 780 points
    Sorry, Typo, I wanted to write:
    To reduce power consumption at standby mode we turn off the TLK2711 Vdd and deactivate the FPGA by pulling down its ProgB pin (its HSWAPEN pin is at "0").
  • 0 in reply to amnon pomerants
    TI__Guru 62930 points
    Amnon,
    can you elaborate what pins will have a voltage applied to them while power is off?
    If it is the inputs, then there is no issue, as the inputs on the TLK2711 are 3.3V tolerant and do not have a VDD component to the absolute max table.

    Regards,
    Wade
  • 0 in reply to Wade Vonbergen
    Intellectual 780 points
    Hello Wade
    I see all SerDes input pins are covered - great.
    Can I please rephrase my question and ask about your general knowledge in this issue, assuming I am asking a theoretical question, about the inputs of any Non "hot insertion" CMOS chip?
    meaning, can you tell me if the above scenario (un loaded FPGA connected to a power down CMOS chip) can harm the CMOS chip inputs (via its clamping diodes etc.) taking into account its weak internal pull up ?

    Thanks
    Amnon
  • 0 in reply to amnon pomerants
    TI__Guru 62930 points
    I can give you some insight.
    There is a specification for this purpose. However, not many (non logic) products will specify this. Traditionally it is call Iik for Input Current Clamp. This specifies a maximum amount of current that can be tolerated when Vi input spec is outside of its abs max range (< gnd or > VCC). For logic products, this is usually +/-25mA. So, you can exceed the Vi abs max spec, if the Iik spec is adhered to.
    Many devices don't specify this current, so exceeding the Vi spec will violate the warranty. Logic products are typically more robust than most other products.

    From a practical standpoint most ESD structures should be able to withstand uA to low mA of current for long periods of time without impacting reliability.
    Another aspect, is back biasing. If an input is driven above VCC with VCC=0, then the input can start to power the internal VCC rails through the ESD diode. For some low power devices, a single input can power up and operate the device. Worse, it could partially power up the device causing nondeterministic behavior or potential stress from improper power on reset.
    Also, if you have more than one weak pullup affecting a device, it should not be an issue for the individual input, but could be an issue for the power up or partial power up with many sourcing small amounts of current to the VCC rail. This can be mitigated with having the unpowered VCC be low impedance to ground to provide path for current without powering up device.

    Hopefully this is helpful.
    Regards,
    Wade