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TLK1501EVM: TLK1501 Startup sequence, error in the order of received data bits

Part Number: TLK1501EVM
Other Parts Discussed in Thread: TLK1501,

Hello,

I asked this question over a year ago.

I have two TLK1501 EVM boards.

Each one has a high precision 62.5 MHZ oscillator with < 20ppm error. Frequency counter measures each one as 62.500000mhz.

The oscillators have an hcmos output sine wave with the ability to drive up to 15 hcmos loads directly. The output 3.3v p-p before being connected to the TLK1501. 

Each board has its own oscillator connected to the GTX-Clock input.

The Oscillator is powered on and enabled before the tlk1501evm 2.5v power is powered up.

The boards are connected to each other via sma cables RXP-RXN to TXP-TXN from board1 to board2.

The boards are jumpered as follows at powerup.

TESTEN - GND

PRBSEN - GND

LOCKREFEN - NO Jumper (high)

ENABLE - NO Jumper (high)

TXER - GND

LOOPEN - GND

TXEN - NO Jumper (high)

SET the TXD0-7 to a pattern of fixed highs and lows with jumpers on or off.

The RX_DV on both board is HIGH. (indicates receive data is valid)

The RX_ER on both boards is LOW. (indicates no receive errors)

The RX_CLK on both boards is good and exactly on frequency. (indicates the clock is being recovered properly from the received data stream)

 

The boards display the data pattern on RD0-7 correctly sometimes and with the bits correct but shifted to other positions. IE, TX0 may show up on RD1 or RD2 or RD8 on the receive board.

The BOTH TLK1501 indicate the DATA IS VALID, and THERE ARE NO RECIEVE ERRORS. The synchronization of the first bit between the boards shifts.

If I remove GTX_Clock briefly from one board, by pulling out j5 briefly, both boards RX_ER will go High, the RX_DV will go low, then go back to RX_ER low and RX_DV high when the clock jumper j5 is reinserted.

This can be just a very brief pull the jumper J5 and immediately reinsert it.

This is a somewhat artificial test because normally both boards would be at a distance and not powered on exactly at the same moment, but it COULD happen coincidently, and I am very concerned about RX_DV data valid flag being high, but the DATA IS NOT VALID.

Can you please help me with this problem ? 

 This has been over a year with no answer ...

I suspect that the power up sequence needs something more than I am doing somehow. 

Thanks > Roger 

 

 

  • Pulling and reseating J5 on ONE of the cards usually resets to data back to the correct bit ordering
  • Hello,

    Just to clarify, are the boards powered simultaneously when you see the bits out of order? If so, have you tired to power them independently?

    Regards,
    Yaser
  • Hello Yaser Ibrahim,

    Thank you for your reply.

    The boards will power up, show data valid and no recieve error but will have the data bits out of alignment SOMETIMES .

    I have tried numerous power up schemes and tried separating the boards in different rooms with the fiber.

    I have ordered two more tlk1501evm boards.

    The documentation indicates that these chips should synchronize themselves at power up and align the data bits properly.  

    Once the data is aligned properly it works without any issues.

    I am suspecting that one of my evm boards may be defective, unless there is some protocol to powering up these chips that is not well documented.

    Thanks again for the help.

  • Hello Berk,

    A couple of things to try.
    1. Change bit pattern of transmitted data (If you haven't done so already) and see if that makes a difference.
    2. At power up, force TLK1501 to send IDLE for longer time by holding TX_EN/TX_ER low.

    Regards,
    Yaser
  • Hello Berk,

    Haven't heard back from you for a while. Do you still need support? I will close this thread at this time, but if you still need support, please respond and the thread will get open again.

    Regards,
    Yaser