SN65DP159: DP159 retimer not giving out clock at AUX_SRCP/N pins when used with Xilinx Displayport RX subsystem v1.2 IP

Varun

Do you have an update to this thread?

Thanks
David

Hello David,

With reference to the slla358, Section 4.5, We do not see the LOCK_COMPLETE bit is set to 1. However we are able to see the I2C write happening in DP159 device.

We were able to get the complete transaction as per Xilinx app note: PG233, Table 3- 1 DP 159 initialization.

One hardware issue in our board we observed was the, Lane0 connection was not as per the reference TI design shown in slla358, Section 2.5

In our design Lane 0 was connected to DP159, pin 8 & 9, where as in reference design Lane0 was connected to  DP159 pin 2&3.

We rewired this Lane0 swap, and we didn't observed no difference in AUX_SRC_P/N line (No Clock), but all status registers were FF, which makes unreliable on PLL lock status also, where "1 is locked". Hence we rolled back to native design.

Could you please help us to proceed further?

Also let us know, when the LOCK_COMPLETE and Clock are driven out by DP159? At which step of DP159 initialization?

Regards,

Varun

Varun

For LOCK_COMPLETE, please refer to section 4.3.1. When DP159 receives the TPS1 (clock) pattern, the SW needs to monitor the PLL_LOCK_COMPLETE status bit.

Besides the steps in section 4.5, please also write 0x00b to Page 1 Addr 0x0Dh and see if there is a clock on AUX.

Thanks
David

Varun

I made a mistake in my previous response, the bit to select between lane 0 and lane 3 is

Page 1 0x0Eh, bit 1
0 – Lane 3 is clock lane
1 – Lane 0 is clock lane

Thanks
David

David,

We are not seeing clock from DP159 after writing to 0x0B to Page 1 0x0Dh register. so we changed this at the initialization step itself (from slla358 section 4. Initial Power-up Configuration). we modified the line

{0x0D, 0x02} , //Select LN0 for clock.

to

 {0x0D, 0x0B} , 

on read of this we could see value 0x03. not sure why 0x0B is not getting reflected here. Can you please help in understanding this register, Is this the Equalization Control Register mentioned in SN65DP159 datasheet? 

DP159 PLL Lock may not have happened but We should be able to see a clock after DP159 initial power-up configuration step. Can you please let us know which register write should have enabled the clock output at AUX_SRCP/N pins

Regards
Varun

Varun

1. Please make sure Lane 0 is connected to IN_D2 or IN_CLK.
2. If Lane 0 is connected to IN_D2, please select Page 1 register by writing to 0x01b to 0xFFh register
3. Please write 0x03b to 0x0Eh register to select LN0 as the clock lane

Thanks
David

David
We have manually wired Lane 0 to IN_D2.
I have written the following to write 0x03 to 0x0E in page1 of DP159, But the value 0x03 is not getting reflected

XDpRxSs_Dp159Write(InstancePtr, XDPRXSS_DP159_IIC_SLAVE, 0xFF, 0x01);
XDpRxSs_Dp159Write(InstancePtr, XDPRXSS_DP159_IIC_SLAVE, 0x0E, 0x03);
XDpRxSs_Dp159Read(InstancePtr, XDPRXSS_DP159_IIC_SLAVE, 0x0E, &Data);
xil_printf("Page1 Address: 0x0E : %d\n\r", Data);

but I could read Page1 Address: 0x0E : 1

Is there something else to be done, I was able to write 0x00 and could it read back, so I guess writes are happening to the register. I was also able to capture the I2C transaction for write on the I2C protocol analyzer.
Please help.

Regards
Varun

David

Do you have an update to this query?

Regards

Varun

Varun

Are you enabling the X-mode?

//Page 0
{0xFF, 0x00} , //Select Page 0
{0x09, 0x36} , //Enable X-Mode

Thanks
David

Varun

Do you have an update to the thread or can we close it?

Thanks
David

David,

Yes we have confirmed this write is happening in the DP159 initialization phase itself, we were able to read back and confirm this. We are still not able to see the clock, strangely we could read lock bit getting asserted. 

Regards

Varun

Varun

Can I please take a look at your schematic? Can you also please capture a scope picture of the input and output clock?

Thanks
David