DS90CR288A: RSKM margin

Toshihiro Watanabe

Part Number: DS90CR288A

Hello

In application note SNLA249, figure 4, TX data toggle at internal Rx clock falling edge then strobe it at internal RX clock rising edge.

If no skew between RxCLKIN and RxIN, Tx send data and clock as the same manner as Figuire 4. Is my understanding correct?

I think the period of setup and hold time of Ideal Rx Strobe position(C area of datasheet figure 16) is below. Is my understanding correct?

C period = [The biggest number of Rsposn min( = the longest number of each bit setup time)] - [The biggest of Rsposn min (= the longest number of each bit hold time)]

We try to calculate the worstest marign of RSKM. I think worst case is Rsposn_max - Tpposn_max but application note used Rsposn_min. Do we misundersatand something?

Best regards,

Toshihiro Watanabe

over 5 years ago

0 Ikechukwu Anyiam over 5 years ago

TI__Mastermind 35130 points

Hi Watanabe-san,

The RSKM is the minimum of the left and right bit margins across all seven bits. You don't really need to calculate the area C since the RSKM, as illustrated in the datasheet and application note, will be the minimum amount of deviation allowed from the ideal strobe position window (area C). This is the value you should work with.

Regards,
I.K.

0 Toshihiro Watanabe over 5 years ago in reply to Ikechukwu Anyiam

TI__Genius 10235 points

Hello Anyiam-san,

Thank you for your reply. We don't need to think all bit error. It is ok to look at each bit individually.

Please let me ask some to understand the operation.

Application note SNLA249 figure 4, ideal Tppos0 is at falling edge of Rx internal clock. ideal Rspos0 is at rising edge of Rx internal clock.

I think the ideal position of internal clock edge is the same position refers to LVDS clock. Because intenal PLL refers this clock. Is my understanding correct?

To think above, Tx device transient data by falling edge, Rx device capture data by rising edge. Is my understanding correct?

I think RSKM is

Ideal period - TX PLL jitter - RX PLL jitter - skew between clock and data

Tx jitter makes position error from ideal position. Rx jitter makes position error from ideal position.

skew between clock and data makes position error between data and clock.

Each factor refers internal PLL so we are ok only see each bit error. This is my understanding.

Please correct me if I am misunderstanding.

Best regards,

Toshihiro Watanabe

0 Ikechukwu Anyiam over 5 years ago in reply to Toshihiro Watanabe

TI__Mastermind 35130 points

Hi Watanabe-san,

The equation for RSKM in the application note is correct. RSKM = min {All Left Bit Margins, All Right Bit Margins}, and you need to calculate the left bit margins and right bit margins based on the minimum/maximum TX pulse positions and Rx strobe positions from the datasheet. It is the maximum amount of skew/jitter that the receiver can tolerate when sampling input data without encountering bit errors.

The internal PLL is a 7x version of the LVDS CLK and determines the strobe positions for the input data.Ideally, each strobe occurs at the center of each data bit, but its position is affected by jitter, temperature drift, skew, etc. Therefore, the ideal strobe position is defined as a window, and the RSKM is the margin available to deviate from this window.

All the information needed to calculate the RSKM is provided in the application note.

Regards,

I.K.

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DS90CR288A: RSKM margin