DS90UB960-Q1: Register settings to be modified when using STP/ Differential mode

Thanks Casey for you reply. I had one more question about the PoC network through FPD-link communication. Is it always necessary to include PoC components in 2G or 4G mode as shown in Fig 41 and Fig 40 if I am using FPD-Link III communication? Can't I omit the PoC network and use FPD-Link III only for forward and backward communication and use an external power supply for DC power for ICs?

Best Regards,

Nishant

Thanks Casey for your answer. Should I still include the AC Coupling cap in the circuit if there is no Poc Network?

Best Regards,

Nishant

Hi Casey,

Thank you for your reply. I had few more questions related to FPD-Link III protocol used in my circuit:

1. I was debugging my FPD-Link III stability by reading UB960 registers and I got the following values:

Value 0x4D: 0x13
Value 0x4E: 0x04 //Sometimes it becomes 0x4d
 Value 0x7A: 0x00 //Sometimes this becomes 0x02, sometimes 0x0e
Value 0x47: 0x00
Value 0x4F: 0x32
Value 0x50: 0x00
Value 0x55: 0x00
Value 0x56: 0x00
 Value 0xD6: 0x00
 Value 0xD7: 0x02

It seems that my FPD-Link is getting locked and is stable but there is some CSI-2 Data packet error in my forward communication. It will be helpful if you could clarify the FPD-link III protocol structure to me. Does it mean that FPD-Link uses some header and footer and contains CSI-2 packets as data while forwarding? If this is the case, then the issue might be in the CSI-2 input data that I am receiving from the radar itself and may not be related to the FPD-Link itself.

2. On debugging the CSI-2 data lines and clock lines with oscilloscope, I observed that the amplitude voltage of the differential clock lines was too low. The amplitude of differential data lines varied from 0-1V while the clock lines were very less, around 150-300 mV. It seemed very abnormal to me. What is the normal voltage you see for differential clock lines in CSI-2 protocol? Is there any reason you think makes the clock amplitude to reduce?

Thank you for your quick responses. I appreciate your help! 

Best Regards,

Nishant

Hello Nishant,

1. It does appear that you are seeing some CSI errors here. I would suggest checking the CSI error registers on the 953 side to see if you can isolate the source of the issue to either the input data from the imager or something related to the high speed FPD Link.

2. CSI-2 uses dynamic termination during data transfer so the amplitude of the CSI-2 lines periodically changes between high and low voltages depending on LP/HS states. You can read more about this in the MIPI CSI-2 or MIPI D-PHY specs. If the clock lane is always low amplitude that means that the clock is in continuous mode, which means it does not periodically transition from LP->HS which means sink terminations are always applied. This is normal and expected behavior.

Best Regards,

Casey 

Hi Casey,

Thank you for this suggestion It helped me in isolating my problem. There was no CSI-2 errors at the UB953 end but the CSI CLK output of UB960 was close to zero. I suspect this is the problem and that's why I am not getting forward data through FPD-Link. I checked my UB960 mode and it was configured correctly for CSI-2 mode( Mode 4). Is there any potential reason why the csi-2 clock voltage is pulled to ground or the voltage swing is going close to zero?

Best Regards,

Nishant

Hello Nishant,

I explained in my previous post that the clock lane swing is very low and this is expected for the MIPI CSI-2 standard. The datasheet gives specs for the voltage swing in the electrical tables. Does your signal meet those specs?

Best Regards,

Casey 

Hi Casey,

Sorry for my delayed and thank you for following up. The issue is definitely on the CSI-2 output CLK from the Deserializer UB960 as I am not meeting the required voltage level of 200mV per differential trace of output CLK. I do not know what is causing this problem. Surprisingly, my board worked perfectly for one time and then it didn't work anytime after that. I do not know how to proceed ahead yet and I am still reading the datasheet of UB960 to try understand the CSI-2 working principle. I am also redesigning my PCB board to have a better impedance matching for my FPD-traces.

Thank you,

Nishant