Part Number: FPC402
Hi Team,
I am working with a customer who is seeing an issue with interfacing an I2C master to the FPC402 as an I2C slave.
Once the master interface is operational, if they reset the I2C master device while they are accessing data from the FPC402, it stops the clock to the slave (FPC402) and the FPC402 waits for the master clock to send the data for the previous read transaction and enters a state where the device is stuck.
As a result, after reboot of the I2C master it cannot access the I2C bus as the SDA line is held low by the slave FPC402 from the previous run.
If they use the P0/P1/P2/P3 Protocol Timout Registers described in Section 2.62 of the datasheet, will this get the device out of the idle state described in this section? If there are any other recovery mechanisms please let me know.
Thanks,
Jeston