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DP83867IR: TskewR of margin

Part Number: DP83867IR

Hi,

Could you let me know about TSkewR in PHY specification? I would like to know margin (Min/Max) of TSkewR about the delay between GTX_CLK and TX_D/CTRL.

According to the specification of RGMII, I think that the delay TskewR between clock and data can be set on PHY side when receiving PHY TX signal.
I found there are uneven in our MAC devices on the sending side. To meet RGMII spec, TskewR in PHY need to be adjusted to absorb this. That is, we want to configure RGMII_RX_DELAY_CTRL is adjusted.
Unfortunately, I think that the data sheet is described RGMII spec but not PHY margin for TX.

Regards,
Kenshow

  • Hi, 

    DP83867 supports non delay and delay mode. In non delay mode, it does not introduce delay between TX_CLK and TX_Dx. In Delay mode, this delay can be configured in granularity of 0.25 ns. Please refer to register 0x0086

    Regards,
    Geet

  • HI Geet,

     I want to know that accuracy of clock delay (MIN/MAX time) when I use delay mode for TskewR in PHY. The default value of RGMII_RX_DELAY_CTRL is 0111b = 2 ns, which specifies the clock delay after data.Then, what is the MIN / MAX time?

    Data sheet is referred to with RGMII spec1.3. It dose not describe the actual value of TskewR, but I think that it indicates the acceptable range in Spec 1.3.

     So, please let me know that the accuracy value (MIN/MAX time) when I set delay mode.

    Regards,
    Kenshow

  • Hi Kenshow,

    Min and Max spec is defined for the Transmitter output (TskewT) and Reciever. Internal delay in range of 0.25ns is speced for typical value only. 

    I recomend refer to below RGMII Delay App Note for more details on how to ensure design meets setup and hold timings at receiver.

    http://www.ti.com/lit/an/snla243/snla243.pdf

    Regards,
    Geet

  • Hi,

    I am closing this thread. Incase you need further assistance, please open new thread and provide reference to this thread.

    Regards,

    Geet