Part Number: DP83867IR
Hi,
Could you let me know about TSkewR in PHY specification? I would like to know margin (Min/Max) of TSkewR about the delay between GTX_CLK and TX_D/CTRL.
According to the specification of RGMII, I think that the delay TskewR between clock and data can be set on PHY side when receiving PHY TX signal.
I found there are uneven in our MAC devices on the sending side. To meet RGMII spec, TskewR in PHY need to be adjusted to absorb this. That is, we want to configure RGMII_RX_DELAY_CTRL is adjusted.
Unfortunately, I think that the data sheet is described RGMII spec but not PHY margin for TX.
Regards,
Kenshow
