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DP83867E: SGMII configuration for internal loopback

Dudi G
Prodigy 70 points
Part Number: DP83867E


Hi,

We have in our board DP83867E which connected through 4 wire SGMII interface to PS_GTR of XILINX ulrtscale+ MPSOC XCZU5EV device.

We are able to control the registers through MDIO interface and we managed to output through CLK_OUT pin 125MHz for the GTR CLK (in between we have a component which converts the single ended 125MHZ to differential LVPECL format for the GTR CLK). I configured the output by changing the value in register 0x170 to 0x80D instead of 0xC0D 

One of my concerns is that maybe we are doing something wrong when configuring the DP83867E PHY to work on loopback with SGMII mode. I used the datasheet instructions along with the SGMII EVB instructions to send set those registers by this order:

 1. SW reset- sent 0x8000 to 0x1F

2. Updated BMCR- sent 0x4140 to 0x00 //Enable loopback, speed 1G, Auto-Negotiation Disabled, full duplex

3. Updated PHYCR- sent 0x5848 to 0x10 //SGMII Enabled

4. Updated LOOPCR- sent 0xE720 to 0xFE //as recommended in DS in case of loopback

5. Updated BISCR- sent 0x04 to 0x16 // for digital loop mode. Tried also to set MII loopback (bit 6)

6. SW restart- sent 0x4000 to 0x1F

Beside those steps, I'm not sure if those registers also need to be changed:

(CFG2, 0x14)- to enable/disable SGMII auto-negotiation and (CFG2, 0x31) to change SGMII_AUTONEG_TIMER 

Another thing, in the datasheet I saw this sentence "Auto-MDIX should be disabled before selecting the Near-End Loopback mode." From which register can I disable the Auto-MDIX? Is that really necessary?

I hope you can help us validate we activated the internal near end loop on the right way so we can continue to investigate why the FPGA doesn't get RX messages from the PHY.

Thanks,

Dudi 

  • 0
    TI__Mastermind 26320 points

    Hi,

    To debug the XLINX RX path, suggest you use only the MAC Loopback which is configured thru BMCR. Besides, ensure you have configured the PHY for SGMII MAC interface. You may also want to check the SGMII link Auto Negotiation is complete.

    You don't need to enable the inner loopback for debbuggin the FPGA-SGMII PHY interface.

    Auto-MDIX can be disabled using register using bit 6 of the PHYCR register (address 0x0010).

    Regards,

    Geet

    Regards,

    Geet

  • 0 in reply to Geet Modi
    Prodigy 70 points

    Hi,

    Thanks for the info. 

    I now do the following steps:

    1. Reset PHY

    2. Change BMCR to be 0x5140 (instead of default value which is 0x1140)- to enable loopback and keep auto negotiation

    3. Validated that PHYCR is OK and defined with SGMII enable (from strap pin) and also that Manual MDI configuration is set (and not MDI-X) .which is bit5 and not bit6 as you mentioned.

    4. Read register 0x37 which shows that SGMII Auto-Negotiation process not complete.

    Any idea why SGMII not completed?  The sequence seems fine? Any other suggestions on how to continue from here?

    FYI- I'm trying to run the test program using XILINX SDK standalone program which uses XEMACPS_exmaple_intr_dma program if you are familiar with.

    Thanks,

    Dudi

  • 0 in reply to Dudi G
    Prodigy 70 points

    Hi again,

    When I read 0x0037 value at the bgining of the code only after power up I see it changes to "2" which means "SGMII page has been received." but not "auto-negotiation complete".

    After that, I can read only "0" at 0x0037 register.

    Another interesting thing- although I define the strap pins correct and RX_CTRL is in mode 3, for some reason I see bit7=1 on register 0x0031 ( I read 0x10B0). Setting this register to 0x1030 doesn't help and still I can't do auto-negotiation.

    When I measure the strap pins at power up I can see that after a while some of them change to 0V (e.g RX_D0, RX_D1, RX_CTRL). Does that make any sense? Maybe the PHY change those pins to strong pull down/ push "0" after configuration is over?

    Please see attached schematic part. Please notice that the power sequence is VDDIO 3.3V EN->waits 40ms-> 2.5V EN-> waits 60ms->1V EN.

    TI_PHY.pdf

    We'll really appreciate quick answers.

    Thank you,

    Dudi

  • 0 in reply to Dudi G
    TI__Mastermind 26320 points

    Hi Dudi,

    In SGMII Auto-Neg sequence,  Phy sends auto neg page with capability and MAC acknowleges. If you are seeing SGMII page is recived, ideally Auto Neg shall complete.

    Few recomenations:

    1. Schematics : I don't see series capacitors but I believe they in the path to MAC.

    2. On layout, I believe lines are differentially routed. 

    3. Register 0x0010, bit[10] indicates SGMII is enabled.

    4. check on MAC side whether it's recieving the SGMII Auto-Neg page and status.

    Regards,
    Geet

  • 0 in reply to Geet Modi
    Prodigy 70 points

    Hi Geet,

    1. Yes. Please see attached scheme area of the MAC connection.

    2. True.

    3. Correct (Please notice it is bit 11 and not 10)

    4. Will do and update you.

    Today I saw that whenever I set the PHY IEEE SW reset (BIT 15 of BMCR) I never get the "SGMII page has been received" message on 0x0037, but instead I read "0".

    Is that reset necessary? (it appears on the original XILINX example) When I cancel it I see as I mentioned "2"- page recieved on 0x0037.

    Thanks,

    Dudi

  • 0 in reply to Dudi G
    TI__Mastermind 26320 points

    On 3, Can you try power cycle and see whether the SGMII Auto Neg page is recieved or not.

    Regards,
    Geet

  • 0 in reply to Geet Modi
    TI__Mastermind 26320 points

    Hi,

    I am closing this thread. Incase you need further assistance, please open new thread and provide reference to this thread.

    Regards,

    Geet