IDCK+ is connected to the FPGA output clock 27Mhz, phase delay DE, HSYNC, VSYNC 270 degrees.
2) Video Sync Configuration
Horizontal sync: 136 pixels (>5000ns)
Horizontal front porch: 24 pixels (>800ns)
Horizontal back porch: 160 pixels (>5900ns)
Vertical sync : 6 lines (>190ms)
vertical front porch: 3 lines (>95ms)
Vertical back porch : 29 lines (>925ms)
At Actual Display Area that DE active
When using TFP410A in this design, the following functions are used:
(1) IIC interface selection: choose to invalidate the IIC interface;
(2) Input bus selection: select 24-bit single clock edge working mode;
(3) Clock synchronization edge selection: select in rising edge mode;
(4) Clock input mode selection: single clock mode;
(5) Selection of clock edge correction function: Select the default setting to enable the clock correction function;
(6) Power down optional function of the chip: select the normal working mode;
(7) Chip input signal level selection: Select low-swing mode.
(1) IIC interface selection: choose to invalidate the IIC interface;
(2) Input bus selection: select 24-bit single clock edge working mode;
(3) Clock synchronization edge selection: select in rising edge mode;
(4) Clock input mode selection: single clock mode;
(5) Selection of clock edge correction function: Select the default setting to enable the clock correction function;
(6) Power down optional function of the chip: select the normal working mode;
(7) Chip input signal level selection: Select low-swing mode.
