RTOS/SN65DSI86: SN65dsi86 DP link training failure .

wenyu Ben

Part Number: SN65DSI86

Tool/software: TI-RTOS

As the last update in case SN65dsi86 DP link training failure .. https://e2e.ti.com/support/interface/f/138/p/802544/2973823#2973823

Please forget bad broken screen issue.

After comfirm , it's due to the cable wrong pin assign to edp lane.

I have replaced a new correct cable , but the semi-auto link failure issue is still as below dump :

2) After I did the DP training twice times , The display is normal work . please give advice ?

Thanks

Ben.

over 6 years ago

0 David (ASIC) Liu over 6 years ago

TI__Guru**** 182001 points

Ben

Can you please try the following?

23 96 02

FF 14

23 96 0A

FF 14

Thanks

David

0 wenyu Ben over 6 years ago in reply to David (ASIC) Liu

Intellectual 500 points

Hi David ,

It's work also .

23 96 02 => TPS1 ? It's for fast-link training mode but seems not used.

But I not understand we did programming register 0x96 two times , that's can pass link training ?

Thanks.

Ben.

0 David (ASIC) Liu over 6 years ago in reply to wenyu Ben

TI__Guru**** 182001 points

Ben

If DP_PLL is enabled and number of DP lanes is non-zero, the DSI86 will start transmitting a data rate random pattern when ML_TX_MODE = 0h. It is best to set ML_TX_MODE to TPS1 so DSI86 is transmitting a known pattern.

Thanks

David

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RTOS/SN65DSI86: SN65dsi86 DP link training failure .