RTOS/SN65DSI86: SN65dsi86 DP link training failure

wenyu Ben

Intellectual 500 points

Part Number: SN65DSI86

Tool/software: TI-RTOS

Hi David ,

Before doing DP link training to assign ML_TX_MODE register with a known pattern can solve this issue.

23 96 02

FF 14

23 96 0A

FF 14

But I have other type of panels that can work without add this --> (23 96 02).

Just want to get more information about "semi-auto link training failure " , Why have the different result ? Thanks.

Thanks.

Ben.

Thanks

Ben.

over 6 years ago

0 David (ASIC) Liu over 6 years ago

TI__Guru**** 177676 points

Ben

Certain panels are more tolerant to the random pattern when ML_TX_MODE = 0h. But it is always a good practice to set the DSI86 register to 23 96 02 to minimize the impact of this random pattern.

Thanks

David

0 wenyu Ben over 6 years ago in reply to David (ASIC) Liu

Intellectual 500 points

Hi David ,

I'm not sure.

Do you mean the random pattern was only given the three patterns for the link training ? If yes , it should has possibility to get training PASS result.

TPS1 , TPS2 , TPS3

Or you mean the pattern is just a random bytes sent out to the DP lanes if DSI86 was first power on.

Below is the Pattern table from dsi86 spec.. :

IDLE
TPS1
TPS2
TPS3
PRBS7 .
HBR2 Compliance Eye
Symbol Error Rate Measurement
80 bit Customer Pattern

Thanks.

Ben.

0 David (ASIC) Liu over 6 years ago in reply to wenyu Ben

TI__Guru**** 177676 points

Ben

Random byte will be sent out, not a known pattern by the DSI86.

Thanks

David

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RTOS/SN65DSI86: SN65dsi86 DP link training failure