DP83867IR: Configure the chip with FPGA,the right flow is?

Hi,

I have used DP83867IRRGZ in my board with MAC  which is soft IP in FPGA.

I want the chip works in RGMII mode,so I configure the register with MDIO ， but it didn‘t work fine.

The configuration flow is below:

(1) Global reset: Set the bit 15 of register 0x001F to '1';

(2) Advertisment the PHY the 1G mode;

(3) LED register configure;

(4)Strap bit clear: clear the the bit7 of register 0x0031;

(5)Enable auto-negotiation: Set the bit 12 of register 0x0000 to '1';

(6) Set PHY to RGMII mode:Set the bit 7 of register 0x0032 to '1';

(7)Set Clock delay with the register 0x0086;

(8) Restart auto-negotiation:Set the bit 9 of register 0x0000 to '1';

(9)Wait the auto-negotiation complete.

Is the configuration flow correct?

Thanks!