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Original question:

DP83640: Question about Application notes from customer

DP83640: Some questions about DP83640

Lin_Charles
Expert 4260 points

Part Number: DP83640

Hi team,

   My customer is using DP83640 to support IEEE1588. This is the same case Sulyn mentioned in the below post, we have below two questions from customer's side,

  • Customer use test method mentioned in snla100a p8 table 1 NO.5, and they find that the master to slave synchronization time peak to peak varies from 1ns to 6ns when power up many times. Is this ok for our device?

  • In the DP838640T device, the internal PTP counter (or digital clock) updates in 8ns increments at a rate of 125 MHz. Will it change to another value when time change? Thanks. 

  

  • 0
    TI__Mastermind 18425 points

    Hi Lin,

    I will get back to you on this by the end of the week.

    -Regards

    Aniruddha

  • 0 in reply to Aniruddha Khadye
    TI__Expert 4260 points

    Hi Aniruddha,

       This is urgent case from customer's side. Please help provide answer to these two questions by 16th Aug. Thanks.

  • 0 in reply to Aniruddha Khadye
    TI__Expert 4260 points

    Hi team,

      Could you please help share me your professional suggestions in this case? Thanks.

  • 0 in reply to Lin_Charles
    TI__Expert 4260 points

    Hi team,

       Any feedback about the questions above? Thanks.

  • 0 in reply to Lin_Charles
    TI__Mastermind 18425 points

    Hi Charles,

    For question 1, the synchronization time variation is a system level question. If the setup measures a variation of 6ns then we will need to ask the customer if it is ok for their application or not. This does not affect the PHY.

    For question 2, are referring to the content of section 4.1

    "PTP Clock: A PTP clock is the source of an output clock signal which is locked to a PTP counter. In the DP83640, the local PTP clock operates at 250 MHz, and can be configured to control the CLK_OUT signal. This PTP CLK_OUT signal is programmable to frequencies which are integral divisions of the 250
    MHz PTP clock in the range of 2 and 255 (125 MHz to 0.98 MHz).


    PTP Counter: A PTP counter contains time information, and is locked to the PTP clock. In a master node, the PTP counter is the source of data used in the Precision Time Protocol for the purpose of synchronizing counters in PTP slave nodes. The PTP counter is incremented every 8 ns."

    This section says that the PTP_CLK_OUT can change from 125MHz to 0.98MHz. However, the PTP clock operates at 250MHz. The PTP counter is tied to PTP Clock and not PTP_CLK_OUT.  As per this information, changing the clock out frequency should not have any effect on the PTP counter increment interval. It should increment every 8ns.

    -Regards

    Aniruddha