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DS80PCI800: DS80PCI800: can not pass PCIE gen 3 eye testing

Kevin.Peng
Intellectual 780 points
Part Number: DS80PCI800
Other Parts Discussed in Thread: DS80PCI810

Hi Team,

DS80PCI800 used on PCI-E riser card applications
When testing the eye diagram and found that PCI-E GEN1 can pass but GEN3 can't pass.

Please refer attached files and help how to adjust the signal to pass GEN3.

Measure the results of PCI-E signal measurements.
Attachment instructions:
Original P0_Math1.html --> Original profile
Original P10_Math1.html --> Original profile

P0 failed eye diagram

P10 failure eye diagram

Adjust EQA1/EQB1=0, EQA0/EQB0=0 to set the result after measurement.

PCIE GEN3 Preset0 mode test eye have open

PCIE GEN3 Preset10 mode test still eye closed

Attachment instructions:

L0P0_Math1.html & L0P0_Math1.html --> Modified profile

Please help how to adjust the signal can pass GEN3.

thanks

Kevin

L0P0_Math1.html 
<html><body><h1> Results for c:\Users\Tek_Local_Admin\Desktop\Gary\CB-1816 A1\CN28\L7\l7\L0P0_Math1 </hs1><hr><p><p><p><font size=4><b><i> Sigtest: </i><font size=3><ul><li>Overall Sigtest Result:<font color=#6633CC> Pass! </font><p><li> Mean Unit Interval (ps): 125.000286<p><li> Min Time Between Crossovers (ps): 84.514544 <br><p><li> Data Rate (Gb/s): 7.999982 <br><p><li> Max Peak to Peak Jitter: 65.796315 ps<br><p><li> Total Jitter at BER of 10E-12: 68.069418 ps<br><font color=#6633CC> Total Jitter at BER of 10E-12 Passes Sigtest Limits! </font><p><li> Minimum eye width: 56.930582 ps<br><p><li> Deterministic Jitter Delta-Delta: 44.664186 ps<br><font color=#6633CC> Deterministic Jitter Delta-Delta Passes Sigtest Limits! </font><p><li> Random Jitter (RMS): 1.664668 ps<br><font color=#6633CC> Random Jitter (RMS) Passes Sigtest Limits! </font><p><li> Minimum Transition Eye Voltage: -0.219711 volts<br><font color=#6633CC> Minimum Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Maximum Transition Eye Voltage: 0.224105 volts<br><font color=#6633CC> Maximum Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Minimum Non Transition Eye Voltage: -0.23286 volts<br><font color=#6633CC> Minimum Non Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Maximum Non Transition Eye Voltage: 0.235951 volts<br><font color=#6633CC> Maximum Non Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Composit Eye Height: 0.075554<p><li> Composit Eye Location: 0.492<br><font color=#6633CC> Composit Eye Height Passes Sigtest Limits! </font><p><li> Minimum Transition Eye Voltage Margin Above Eye: 0.018971 volts<br><font color=#6633CC> Minimum Transition Eye Voltage Margin Above Eye Passes Sigtest Limits! </font><p><li> Minimum Transition Eye Voltage Margin Below Eye: -0.016388 volts<br><font color=#6633CC> Minimum Transition Eye Voltage Margin Below Eye Passes Sigtest Limits! </font><p><li> Minimum Transition Eye Height: 0.081358 volts<br> <p><li> Minimum Non Transition Eye Voltage Margin Above Eye: 0.070741 volts<br><font color=#6633CC> Minimum Non Transition Eye Voltage Margin Above Eye Passes Sigtest Limits! </font><p><li> Minimum Non Transition Eye Voltage Margin Below Eye: -0.074669 volts<br><font color=#6633CC> Minimum Non Transition Eye Voltage Margin Below Eye Passes Sigtest Limits! </font><p><li> Minimum Non Transition Eye Height: 0.19141 volts<br>  <br></ul><hr><p><i>Worst Non Transition Signal Eye</i><p><img src=".\L0P0_Math1Eye.png"></body></html> <br></ul><hr><p><i>Worst Transition Signal Eye</i><p><img src=".\L0P0_Math1TransitionEye.png"></body></html></font><p>TEMPLATE FILE SETTINGS<p><li> Template File: PCIE_3_0_SYS \ PCIE_3_8GB_CEM_DUAL_PORT<p><li> Nominal Data Rate (bits/sec): 8000000000.0<p><li> Target Unit Interval (s): 1.25e-010<p><li> Minimum Time Allowed Between Crossovers (s): 7.5e-011<p><li> Minimum Data For Testing (UI): 200<p><li> Ambiguous UI Resolution Method: EYE_AMBIGUOUS_NONE (0)<p><li> Tj@E-12 Peak to Peak Jitter Limit (s): 8.375e-011<p><li> Rj (RMS) Jitter Limit (s): 3.0e-012<p><li> CTLE equalization index = 7<p><li> DFE equalization: Tap 1 = -5.311185, Tap 2 unused<p><li> Compliance pattern preset = 0<p><li> Compliance pattern lane = 0<p>Sigtest Version: 3.2.11
L0P10_Math1.html 
<html><body><h1> Results for c:\Users\Tek_Local_Admin\Desktop\Gary\CB-1816 A1\CN28\L7\l7\L0P10_Math1 </hs1><hr><p><p><p><font size=4><b><i> Sigtest: </i><font size=3><ul><li>Overall Sigtest Result:<font color=#CC0033> Fail! </font><p><li> Mean Unit Interval (ps): 125.000314<p><li> Min Time Between Crossovers (ps): 93.304251 <br><p><li> Data Rate (Gb/s): 7.99998 <br><p><li> Max Peak to Peak Jitter: 1172.973743 ps<br><p><li> Total Jitter at BER of 10E-12: 2085.959448 ps<br><font color=#CC0033> Total Jitter at BER of 10E-12 Fails Sigtest Limits! </font><p><li> Minimum eye width: -1960.959448 ps<br><p><li> Deterministic Jitter Delta-Delta: -679.481091 ps<br><font color=#6633CC> Deterministic Jitter Delta-Delta Passes Sigtest Limits! </font><p><li> Random Jitter (RMS): 196.688516 ps<br><font color=#CC0033> Random Jitter (RMS) Fails Sigtest Limits! </font><p><li> Minimum Transition Eye Voltage: -0.204667 volts<br><font color=#6633CC> Minimum Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Maximum Transition Eye Voltage: 0.20721 volts<br><font color=#6633CC> Maximum Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Minimum Non Transition Eye Voltage: -0.212364 volts<br><font color=#6633CC> Minimum Non Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Maximum Non Transition Eye Voltage: 0.213556 volts<br><font color=#6633CC> Maximum Non Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Composit Eye Height: 9.566975e-007<p><li> Composit Eye Location: 0.5<br><font color=#CC0033> Composit Eye Height Fails Sigtest Limits! </font><p><li> Minimum Transition Eye Voltage Margin Above Eye: -0.023 volts<br><font color=#CC0033> Minimum Transition Eye Voltage Margin Above Eye Fails Sigtest Limits! </font><p><li> Minimum Transition Eye Voltage Margin Below Eye: 0.023 volts<br><font color=#CC0033> Minimum Transition Eye Voltage Margin Below Eye Fails Sigtest Limits! </font><p><li> Minimum Transition Eye Height: 0.0 volts<br> <p><li> Minimum Non Transition Eye Voltage Margin Above Eye: -0.023 volts<br><font color=#CC0033> Minimum Non Transition Eye Voltage Margin Above Eye Fails Sigtest Limits! </font><p><li> Minimum Non Transition Eye Voltage Margin Below Eye: 0.023 volts<br><font color=#CC0033> Minimum Non Transition Eye Voltage Margin Below Eye Fails Sigtest Limits! </font><p><li> Minimum Non Transition Eye Height: 0.0 volts<br>  <br></ul><hr><p><i>Worst Non Transition Signal Eye</i><p><img src=".\L0P10_Math1Eye.png"></body></html> <br></ul><hr><p><i>Worst Transition Signal Eye</i><p><img src=".\L0P10_Math1TransitionEye.png"></body></html></font><p>TEMPLATE FILE SETTINGS<p><li> Template File: PCIE_3_0_SYS \ PCIE_3_8GB_CEM_DUAL_PORT<p><li> Nominal Data Rate (bits/sec): 8000000000.0<p><li> Target Unit Interval (s): 1.25e-010<p><li> Minimum Time Allowed Between Crossovers (s): 7.5e-011<p><li> Minimum Data For Testing (UI): 200<p><li> Ambiguous UI Resolution Method: EYE_AMBIGUOUS_NONE (0)<p><li> Tj@E-12 Peak to Peak Jitter Limit (s): 8.375e-011<p><li> Rj (RMS) Jitter Limit (s): 3.0e-012<p><li> CTLE equalization index = 1<p><li> DFE equalization: Tap 1 = -10.080624, Tap 2 unused<p><li> Compliance pattern preset = 10<p><li> Compliance pattern lane = 0<p>Sigtest Version: 3.2.11

original P0_Math1.html 
<html><body><h1> Results for c:\Users\Tek_Local_Admin\Desktop\Gary\CB-1816 A1\CN28\L0\P0_Math1 </hs1><hr><p><p><p><font size=4><b><i> Sigtest: </i><font size=3><ul><li>Overall Sigtest Result:<font color=#CC0033> Fail! </font><p><li> Mean Unit Interval (ps): 125.000348<p><li> Min Time Between Crossovers (ps): 96.710924 <br><p><li> Data Rate (Gb/s): 7.999978 <br><p><li> Max Peak to Peak Jitter: 284.311916 ps<br><p><li> Total Jitter at BER of 10E-12: 359.177952 ps<br><font color=#CC0033> Total Jitter at BER of 10E-12 Fails Sigtest Limits! </font><p><li> Minimum eye width: -234.177952 ps<br><p><li> Deterministic Jitter Delta-Delta: 167.957506 ps<br><font color=#6633CC> Deterministic Jitter Delta-Delta Passes Sigtest Limits! </font><p><li> Random Jitter (RMS): 13.600316 ps<br><font color=#CC0033> Random Jitter (RMS) Fails Sigtest Limits! </font><p><li> Minimum Transition Eye Voltage: -0.343506 volts<br><font color=#6633CC> Minimum Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Maximum Transition Eye Voltage: 0.341976 volts<br><font color=#6633CC> Maximum Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Minimum Non Transition Eye Voltage: -0.358157 volts<br><font color=#6633CC> Minimum Non Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Maximum Non Transition Eye Voltage: 0.361277 volts<br><font color=#6633CC> Maximum Non Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Composit Eye Height: 1.672845e-005<p><li> Composit Eye Location: 0.5<br><font color=#CC0033> Composit Eye Height Fails Sigtest Limits! </font><p><li> Minimum Transition Eye Voltage Margin Above Eye: -0.022994 volts<br><font color=#CC0033> Minimum Transition Eye Voltage Margin Above Eye Fails Sigtest Limits! </font><p><li> Minimum Transition Eye Voltage Margin Below Eye: 0.023006 volts<br><font color=#CC0033> Minimum Transition Eye Voltage Margin Below Eye Fails Sigtest Limits! </font><p><li> Minimum Transition Eye Height: 0.0 volts<br> <p><li> Minimum Non Transition Eye Voltage Margin Above Eye: -0.022984 volts<br><font color=#CC0033> Minimum Non Transition Eye Voltage Margin Above Eye Fails Sigtest Limits! </font><p><li> Minimum Non Transition Eye Voltage Margin Below Eye: 0.023016 volts<br><font color=#CC0033> Minimum Non Transition Eye Voltage Margin Below Eye Fails Sigtest Limits! </font><p><li> Minimum Non Transition Eye Height: 0.0 volts<br>  <br></ul><hr><p><i>Worst Non Transition Signal Eye</i><p><img src=".\P0_Math1Eye.png"></body></html> <br></ul><hr><p><i>Worst Transition Signal Eye</i><p><img src=".\P0_Math1TransitionEye.png"></body></html></font><p>TEMPLATE FILE SETTINGS<p><li> Template File: PCIE_3_0_SYS \ PCIE_3_8GB_CEM_DUAL_PORT<p><li> Nominal Data Rate (bits/sec): 8000000000.0<p><li> Target Unit Interval (s): 1.25e-010<p><li> Minimum Time Allowed Between Crossovers (s): 7.5e-011<p><li> Minimum Data For Testing (UI): 200<p><li> Ambiguous UI Resolution Method: EYE_AMBIGUOUS_NONE (0)<p><li> Tj@E-12 Peak to Peak Jitter Limit (s): 8.375e-011<p><li> Rj (RMS) Jitter Limit (s): 3.0e-012<p><li> CTLE equalization index = 7<p><li> DFE equalization: Tap 1 = -25.393572, Tap 2 unused<p><li> Compliance pattern preset = 0<p><li> Compliance pattern lane = 0<p>Sigtest Version: 3.2.11
original P10_Math1.html 
<html><body><h1> Results for c:\Users\Tek_Local_Admin\Desktop\Gary\CB-1816 A1\CN28\L0\P10_Math1 </hs1><hr><p><p><p><font size=4><b><i> Sigtest: </i><font size=3><ul><li>Overall Sigtest Result:<font color=#CC0033> Fail! </font><p><li> Mean Unit Interval (ps): 125.000335<p><li> Min Time Between Crossovers (ps): 100.790799 <br><p><li> Data Rate (Gb/s): 7.999979 <br><p><li> Max Peak to Peak Jitter: 775.24782 ps<br><p><li> Total Jitter at BER of 10E-12: 1416.638235 ps<br><font color=#CC0033> Total Jitter at BER of 10E-12 Fails Sigtest Limits! </font><p><li> Minimum eye width: -1291.638235 ps<br><p><li> Deterministic Jitter Delta-Delta: -382.235949 ps<br><font color=#6633CC> Deterministic Jitter Delta-Delta Passes Sigtest Limits! </font><p><li> Random Jitter (RMS): 127.942687 ps<br><font color=#CC0033> Random Jitter (RMS) Fails Sigtest Limits! </font><p><li> Minimum Transition Eye Voltage: -0.337965 volts<br><font color=#6633CC> Minimum Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Maximum Transition Eye Voltage: 0.334648 volts<br><font color=#6633CC> Maximum Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Minimum Non Transition Eye Voltage: -0.350893 volts<br><font color=#6633CC> Minimum Non Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Maximum Non Transition Eye Voltage: 0.355698 volts<br><font color=#6633CC> Maximum Non Transition Eye Voltage Passes Sigtest Limits! </font><p><li> Composit Eye Height: 2.120859e-006<p><li> Composit Eye Location: 0.5<br><font color=#CC0033> Composit Eye Height Fails Sigtest Limits! </font><p><li> Minimum Transition Eye Voltage Margin Above Eye: -0.023001 volts<br><font color=#CC0033> Minimum Transition Eye Voltage Margin Above Eye Fails Sigtest Limits! </font><p><li> Minimum Transition Eye Voltage Margin Below Eye: 0.022999 volts<br><font color=#CC0033> Minimum Transition Eye Voltage Margin Below Eye Fails Sigtest Limits! </font><p><li> Minimum Transition Eye Height: 0.0 volts<br> <p><li> Minimum Non Transition Eye Voltage Margin Above Eye: -0.023 volts<br><font color=#CC0033> Minimum Non Transition Eye Voltage Margin Above Eye Fails Sigtest Limits! </font><p><li> Minimum Non Transition Eye Voltage Margin Below Eye: 0.023 volts<br><font color=#CC0033> Minimum Non Transition Eye Voltage Margin Below Eye Fails Sigtest Limits! </font><p><li> Minimum Non Transition Eye Height: 0.0 volts<br>  <br></ul><hr><p><i>Worst Non Transition Signal Eye</i><p><img src=".\P10_Math1Eye.png"></body></html> <br></ul><hr><p><i>Worst Transition Signal Eye</i><p><img src=".\P10_Math1TransitionEye.png"></body></html></font><p>TEMPLATE FILE SETTINGS<p><li> Template File: PCIE_3_0_SYS \ PCIE_3_8GB_CEM_DUAL_PORT<p><li> Nominal Data Rate (bits/sec): 8000000000.0<p><li> Target Unit Interval (s): 1.25e-010<p><li> Minimum Time Allowed Between Crossovers (s): 7.5e-011<p><li> Minimum Data For Testing (UI): 200<p><li> Ambiguous UI Resolution Method: EYE_AMBIGUOUS_NONE (0)<p><li> Tj@E-12 Peak to Peak Jitter Limit (s): 8.375e-011<p><li> Rj (RMS) Jitter Limit (s): 3.0e-012<p><li> CTLE equalization index = 7<p><li> DFE equalization: Tap 1 = -28.984696, Tap 2 unused<p><li> Compliance pattern preset = 10<p><li> Compliance pattern lane = 0<p>Sigtest Version: 3.2.11

DS80PCI800 SCH.pdf

  • 0
    TI__Mastermind 43795 points

    Hi Kevin,

    The DS80PCI800 will not be able to pass open eye waveforms with all Tx Presets.  In your application P0 (nominal -6dB) is producing an open eye and a slight amount of overequalization with the minimum DS80PCI800 equalization settings.  It is likely that other presets (P2 and P1) will also produce an open eye.  P3 and P4 will likely need a slight increase in DS80PCI800 equalization to produce a similar eye opening. 

    P10 is rarely going to produce an open eye.  It is primarily used to test the Transmit equalization levels only.

    You could switch over to the DS80PCI810 and more of the Tx presets could achieve an open eye since this newer device has improved linearity and lower overall gain which would work well in this application.

    Regards,

    Lee

  • 0 in reply to Lee Sledjeski
    Intellectual 780 points

    Hi Lee,

    This's project to be mass-produced.

    Is the DS80PCI810 a direct replacement and not need change the BOM?

    Is there any suggestion for EQ settings?

    thanks

    Kevin

  • 0 in reply to Kevin.Peng
    Intellectual 780 points

    Hi Lee,

    I have some confusing, the GEN3 P10 is a standard test item. if this P10 can not open eye,
    Does that mean that the DS80PCI800 does not support P10 pass item?
    If yes, is there a statement document?
    Because this is a mass production project, it is somewhat difficult to change parts.

    thanks

    Kevin

  • 0 in reply to Kevin.Peng
    Intellectual 780 points

     

    Hi Lee,

    Because this case urgently needs to be solved!

    How does the DS80PCI800 improve the P10 mode open eye?
    If the DS80PCI810 is recommended to replace, does it mean that the DS80PCI800 is a bug?

    thanks

    Kevin

  • 0 in reply to Kevin.Peng
    TI__Mastermind 43795 points

    Hi Kevin,

    The DS80PCI800 is not broken.  It will meet the eye requirements with several Tx Presets.  P10 is not considered a useful Tx equalization for an actual system implementation.

    This text is from the CEM specification.

    Base Specification. A motherboard must meet eye diagram requirements in Chapter 9 at 8.0 GT/s and 16.0 GT/s on each lane with one or more preset equalization setting.

    A system board shall meet the following additional rules for this specification:

    •  The system board initial TX preset at 8.0 GT/s shall be P1, P7, or P8.
    • If the equivalent of the ps21 parameter defined in the PCI Express Base Specification, measured at data rates of 8.0 GT/s at the end of the 5.0 GT/s System-Board Test Channel without de-embedding shows a loss of more than 12 dB, then the system board initial TX preset at 8.0 GT/s shall be P7 or P8.

     

     

    Regards,

    Lee

  • 0 in reply to Lee Sledjeski
    Intellectual 780 points

    Hi Lee

    Today, I confirm that the customer is using the DS80PCI810NJY unit.

    Schematic is marked incorrectly and not DS80PCI800. I'm a bit confused, sorry.
    As shown in the photo


    Now using the DS80PCI810 for Riser Card, because not recognize the external card when insert the Riser Card.

    If do not install the Riser Card, only use the PCI-E slot of the motherboard can to recognize the external card.
    Therefore,To measure the P10 mode found without opening eyes.
    How can the DS80PCI810 be adjusted to open eyes through P10 mode?
    please help

    thanks

    Kevin

  • 0 in reply to Kevin.Peng
    TI__Mastermind 43795 points

    Kevin,

    Using the DS80PCI810 should make things easier.

    Without knowing the channel attenuation around the DS80PCI810 I would start using these settings.

    ENSMB = 0

    EQA/B = 0 (minimum)

    VODA1/VODB1 = 1

    VODA0/VODB0 = 0  (Level 6)

    For SMBus Slave configuration:

    ENSMB = 1

    Write Register 0x06 = 18'h

    Write Registers 0x0F, 0x16, 0x1D, 0x24, 0x2C, 0x33, 0x3A, 0x41 = 00'h

    Write Registers 0x11, 0x18, 0x1F, 0x26, 0x2E, 0x35, 0x3C, 0x43 = 00'h  

  • 0 in reply to Lee Sledjeski
    TI__Mastermind 43795 points

    Hi Kevin,

    Did you try the configuration settings I sent?

    Regards,

    Lee