SN75DP130: Transparent mode for analog parameter settings

Joe

The DP130 monitors the AUXto DisplayPort Configuration Data (DPCD) registers during Link Training in DP mode to select the output voltage swing VOD, output pre-emphasis, and the EQ setting of the Main Link. But you can choose to disable link training in DP130, have the FPGA manually generate the data pattern and then manually configure DP130 RX equalizer, and TX VOD and pre-emphasis level.

Thanks

David 

Hi David,

that was what I tried at first. Our sequence was:

DPout,04,00,DP_TX training dissable,

DPout,1c,00,High address        LINK_BW_SET,
DPout,1d,01,Medium address  LINK_BW_SET,
DPout,1e,00,Low address        LINK_BW_SET,
DPout,1f,14,Data                      5.4G,

DPout,1c,00,High address       LANE_COUNT_SET,
DPout,1d,01,Medium address  LANE_COUNT_SET,
DPout,1e,01,Low address        LANE_COUNT_SET,
DPout,1f,04,Data                     4 Lanes,

DPout,1c,00,High address        L0,
DPout,1d,01,Medium address  L0,
DPout,1e,03,Low address        L0,
DPout,1f,01,Data                     Swing_LVL_1,

DPout,1c,00,High address        L1,
DPout,1d,01,Medium address  L1,
DPout,1e,04,Low address        L1,
DPout,1f,01,Data                      Swing_LVL_1, 

DPout,1c,00,High address        L2,
DPout,1d,01,Medium address  L2,
DPout,1e,05,Low address        L2,
DPout,1f,01,Data                      Swing_LVL_1,     

DPout,1c,00,High address        L3,
DPout,1d,01,Medium address  L3,
DPout,1e,06,Low address        L3,
DPout,1f,01,Data                      Swing_LVL_1, 

DPout,1c,00,High address        MODE,
DPout,1d,06,Medium address  MODE,
DPout,1e,00,Low address        MODE,
DPout,1f,01,Data                      NORMAL_OPERATION, 

DPout,03,00,                             Squelch dissable,
DPout,05,80,                             Enable equalization from I2C - not needed,

DPout,05,B3,                             Enable equalization from I2C L0, 
DPout,07,33,                             Enable equalization from I2C L1,
DPout,09,33,                             Enable equalization from I2C L2,
DPout,0B,33,                            Enable equalization from I2C L3,

am I doing something wrong ?

I also can read from manual (http://www.ti.com/lit/ds/symlink/sn75dp130.pdf) page 21 that read value from DPCD 101h should be 02h for four lines but sink UG (http://www.ti.com/lit/an/slla349/slla349.pdf) page 5 tells that I should get 0Fh so whats rigth ? 

Joe

Please try to disable the squelch by writing the value of 0x08 to register 0x0x3h. 

Where do you see reading 0x02 for 4 lanes in the datasheet?

Do you have HPD_SNK going high?

Thanks

David