TMDS171: TMDS171 : DDC- SCL_SRC -> SCL_SNK freqency change in source side application (2)

Akihisa Tamazaki

Part Number: TMDS171

David-san, JMMN-san,

The customer has related questions from the following E2E.
https://e2e.ti.com/support/interface/f/138/t/836082

Now, the customer use default setting of both registers (0Bh, bit 02, 100ksps, 09h bit(1:0) 100ksps), now.

Q1) In above setting, can we use 400kHz signal from HDMI Tx? If not, what happn?
Q2) Should we set both (0Bh bit2 and 09h bit(1:0) ) registers when 400kHz signal is used?

Your advise would be so appreciated.

Best Regards,
Akihisa Tamazaki

over 5 years ago

0 David (ASIC) Liu over 5 years ago

TI__Guru**** 176281 points

Akihisa-san

The DDC link of the TMD171 defaults to 100 kbps but can be set to various values including 400 kbps by setting the correct value to address 0Bh through the I 2C interface.

Please note that the HPD_AUTO_PWRDWN_DISABLE bit must be set before enabling the 400 kbps.

Thanks

David

0 Akihisa Tamazaki over 5 years ago in reply to David (ASIC) Liu

TI__Genius 12410 points

David-san,

Thank you for your comment.

I have additional questions.
I will ask you on offline because it is including the customer information.

Your cooperation would be so appreciated.

Best Regards,
Akihisa Tamazaki

Interface

Interface forum

TMDS171: TMDS171 : DDC- SCL_SRC -> SCL_SNK freqency change in source side application (2)