Hello,
A customer of mine has two questions that they cannot find in the datasheet:
1-) Latency Info for SGMII is missing.
Phy has interface with FPGA. It can either be RGMII or SGMII. Both interfaces have advantages and disadvantages, according to FPGA pin count and latency requirements, we would like to use them both.
For Latency requirements, we found the latency data for RGMII but we couldn’t find it for SGMII, which is very important for us to calculate the total latencies in our system.
2-) Three Supply Mode Power up Sequence
Phy can operate with 2 or 3 supplies. For 2 supply mode, there is no power sequence required. For 3 supply mode, there is a requirement which is not totally clear for me.
For 2 supplies mode, power consumption of the PHY is a bit higher than 3 supplies mode. On one of our boards, We are going to have 21 of these PHYs so power consumption is important for this design.
In datasheet it is stated as, 1V8 needs to ramp up in 25ms after 2V5 is stable. On the other hand, it is also stated as, if 2V5 only feeds PHY chip, 1V8 needs to ramp up anytime before 2V5 ramps up.
The proposal is clear but it is very strange, because they are opposed to each other.
Hope you can help us here.
Thank you!
