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Original question:

DS90UB934-Q1: Camera sync and multiplexing

DS90UB933-Q1: HSYNC and VSYNC width

Xiao Zhu2
Expert 3215 points
Part Number: DS90UB933-Q1

Hello Team

Does DS90UB933 requirement for the minimum high width for  HSYNC and VSYNC? for examle, 1 PCLK or  2PCLK?

  • 0
    TI__Mastermind 25955 points

    Hi Xiao,

    Great question!  For the DS90UB933-Q1, the HSYNC and VSYNC do not have transition restrictions in 12 bit mode (raw), however, when in 10 bit mode HSYNC and VSYNC are restricted to no more than 1 transition per 10 PCLK cycles.

    In 10 bit mode, the minimum width allowable by the interface would be 10 PCLK cycles. In 12 bit mode the minimum width allowable by the interface would be 1 PCLK, however, this is not often seen in practice because the minimum permissible width is usually dictated by the devices coupled to the interface.

    Sincerely,
    Bryan Kahler

  • 0 in reply to Bryan Kahler
    TI__Mastermind 25955 points

    Hi Xiao,

    Haven't heard from you in a while - hopefully no news is good news and the issue is now resolved.  If so, to help enable others that may have the same question find the correct answer, please press the green 'this resolved my issue' button.

    If not, please let me know what other issues remain.

    Sincerely,
    Bryan Kahler