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DS90UB941AS-Q1: The output display of DS90UB941+DS90UB948 connected to 1920x720 screen is abnormal

Amy Luo
Expert 6895 points
Part Number: DS90UB941AS-Q1
Other Parts Discussed in Thread: DS90UB948-Q1,

Hi team,

My customer has the following problems, which are described in Chinese. I am not familiar with SerDes products. I translate the questions from Chinese to English. If you are confused, please point out.

At present, the scenarios used in the project are as follows:

Using DS90UB941AS-Q1+DS90UB948-Q1, the display screen is dual LVDS 1920x720 resolution, the MIPI input of SOC on 941 is connected to DSI0, MIPI is 4lane, 941 and 948 direct link are Dual-Link mode.

941 uses the following configuration:

WriteI2C( 0x01, 0x82);

WriteI2C( 0x5B, 0x03);

WriteI2C(0x56, 0x01);
WriteI2C(0x03, 0xBA);
WriteI2C(0x1E, 0x01); 

WriteI2C( 0x40, 0x04); 
WriteI2C( 0x41, 0x21); 
WriteI2C( 0x42, 0x60);

WriteI2C( 0x40, 0x04); 
WriteI2C( 0x41, 0x05); 
WriteI2C( 0x42, 0x1E); 

WriteI2C( 0x01, 0x00);

There is no special configuration in 948, just a few GPIOs for lighting the screen.

The existing problems are as follows:

1. Test the external 85m active crystal oscillator

Test mode is configured on ds941, and test colorbar is output on 948. If 0x65 is configured as 0xc, test picture can be output normally; if 0x65 is configured as 0x8, test picture cannot be output.

When external crystal oscillator is used, DSI signal input source is used, and there is no image display on LVDS screen.

2. Test and use DSI clock source

If the clock source is configured as DSI on ds941, 0x65 is configured as 0xc or 0x8, colorbar cannot be output on 948, and the lock pin of 948 outputs a 60Hz pulse signal.

In addition, for the test picture used, the customer configured it to output 1920x720 resolution. MIPI output configuration is also 1920x720.

Best Regards,
Amy Luo

  • 0
    TI__Guru** 103215 points

    Hello Amy,

    Thank you for providing all the details. In order to better assist can you also please help clarify a couple more points?

    - What is the target PCLK value for the display?

    - What is the MIPI DSI data rate being used?

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    TI__Expert 6895 points

    Hi Casey,

    Thanks for your response.

    As for the two problems you mentioned, the customer seems to have new problems, as follows:

    1. The target PCLK value for the display is given as 44M-61M in the specification. As shown in the figure below：

    2. For the data rate of MIPI DSI used, the parameters of MIPI DSI at SOC end are as follows:

    It supports 2 channels 4-lane MIPI DSI, the maximum speed of each group is 2.1Gbps, and supports dual screen display.

    MIPI DSI rate can be configured according to the parameters of display settings. For example, when 1920x720 30fps is configured, the data rate of MIPI DSI is calculated as follows:

    In the current debugging, it is found that when the output of SOC configured MIPI DSI exceeds 1920 x 720, 30fps, the 948 terminal LVDS CLK clock output is high.When 1920x720 25FPS is configured, the LVDS CLK output of 948 terminal is 19.6MHZ.

    Best Regards,
    Amy Luo

  • 0 in reply to Amy Luo
    TI__Guru** 103215 points

    Hello Amy,

    First please measure the input DSI clock frequency to the 941AS to confirm the frequency. It sounds like the programmed DSI clock value may not be coming out as expected. Also please double check if you have 948 in dual OLDI mode of single OLDI mode. In dual OLDI mode there are two clocks transmitting even and odd pixels separately to the panel so the measured PCLK at the output of either one will be 1/2 the total PCLK for the image. 

    Best Regards,

    Casey