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Tool/software:
The DS90UB941 configuration register combined with the DS90UB948 outputs 1920*1080 images,
But refer to the programming example of zhcaag5a.pdf manual to modify, the specific register is written as follows, but it can not be displayed on the screen, and read 0x06 register through 941 address can not read the address of the unstring 948, directly read with 948 address, The returned status value is STATUS_I2C_RECEIVED_NACK, there is no idea, please guide to deal with it, thank you
1. 941 and 948 can be locked after power-on, but TI941_WriteRegister(IDX_941, 0x01, 0x08) when starting to configure the 941 register; And TI941_WriteRegister(IDX_941, 0x4F, 0xDC); So the register will cause the Lock to disconnect, and can not restore the normal connection state, why?
2. According to your above Pointers, reconfigure the register 0x41,0x42, then how to configure the corresponding relevant data, because I did not find the reference article, I finally need to output is 1920*1080 screen
Hello!
941 and 948 can be locked after power-on, but TI941_WriteRegister(IDX_941, 0x01, 0x08) when starting to configure the 941 register; And TI941_WriteRegister(IDX_941, 0x4F, 0xDC); So the register will cause the Lock to disconnect, and can not restore the normal connection state, why?
Yes, this is expected behavior, the first write (0x01=0x08) disables the DSI input, the second write sets the DSI configuration. While the DSI is disabled, there is no input to the RX of the 941 SER, meaning no valid video throughput to the 948.
At this time, the 948 will sample whether valid video is incoming to certify whether lock is established based on register 0x34 bit 6: RX_LOCK_MODE
This explains why the lock status is not established as DSI is being configured.
According to your above Pointers, reconfigure the register 0x41,0x42, then how to configure the corresponding relevant data, because I did not find the reference article, I finally need to output is 1920*1080 screen
I recommend referring to the DS90UB941AS-Q1 DSI Bringup Guide for specific configuration assistance, as I see splitter mode is being implemented here with cropping to two displays.
In the debug section, it is recommended to first test the internal pattern generation in order to certify the connection from SER -> DES -> Display is working appropriately, in a topology of SER -> DES -> x1 Display at 1920x1080p, a pattern script can be generated with the register assignments in Exploring the Int Test Pattern Generation Feature of FPD-Link III IVI Devices (Rev. G).
If you need, I can help generate this script, but I believe the pattern generated will only go to one display (in which I will need the display specification for all timing parameters).
Please let me know what assistance you may need from here!
Best,
Miguel
At present, according to the configuration in the figure, the screen can be displayed, but there is a flower screen, can you help to see is the register configuration cause flower screen? Checked the hardware and found no problems. Thank you
Hello!
I can help you evaluate this configuration; can you please provide an example of flower screen or describe the exact abnormality for documentation purposes?
Per the debugging flow of the bring up guide (https://www.ti.com/lit/an/snla356/snla356.pdf?ts=1740076915839), I am providing a PATGEN script, which will be internally generated through the 941AS send directly to the 948. Can you please double confirm the topology used by providing a block diagram?
1920*1080 is the image output, and the clock frequency is 142MHz-158MHz
I may also need the display timing specifications to prevent any issues from the video timing on the display side, but I have provided a default 1920 x 1080 resolution at 60 fps (148.5 MHz PCLK) PATGEN.
Please refer to the script below for these register writes:
In this case, you may replace devAddr with IDX_941 as used in your script.
For further clarification on these configuration registers, please see Exploring the Int Test Pattern Generation Feature of FPD-Link III IVI Devices (Rev. G)
Since PATGEN will be internally generated at the 941, there is no need for DSI configuration at this time - we are testing the link between SER -> DES -> Display independent of the source.
Please let me know the results of the testing, then we can proceed to next steps to resolve display abnormalities.
Thanks,
Miguel
1、Our project is to input MIPI to LVDS output 1920*1080. Through the example of output internal color bar chart provided by you, the color bar chart can be output normally after testing.1920*1080 is the image output, and the clock frequency is 142MHz-158MHz;
2、The above is my configuration of the 941 register, through the above configuration, the output screen appears flower screen;
3、In order to be able to output 1920*1080 video normally, how should I configure, please guide me, more eager，thank you!
Hello,
Thanks for this information, we will need this for a later step in the debug.
Through the example of output internal color bar chart provided by you, the color bar chart can be output normally after testing.1920*1080 is the image output, and the clock frequency is 142MHz-158MHz
For the time being we can now proceed with the flow diagram now that PATGEN from SER is successful (from DS90UB941AS-Q1 DSI Bringup Guide):
The next script will confirm if the clock is correct and using internal timing (data lanes are not applied).
While the DSI source is enabled, it will only be providing clock in this scenario, as options of External Clock Source is enabled and Timing is generated and configured internally.
Please let me know the results of this test, and we may proceed with understanding where the phenomenon is occurring from.
Best,
Miguel
Hi,
Let us try using this same script by not disabling the clock -> this TX of the DSI is needed to configure the PATGEN:
The PGTSC was not carried over from the previous write as 0x21 - this is corrected (but has no effect, as auto scrolling is disabled).
Since the DSI configuration is not disturbed in this setup, please try this sequence:
This comes from 941 power up sequencing, the suggestion here is to apply the DSI input before initializing with the code above to see if the output will appear. In this way, we can rule out whether the DSI clock is part of the issue in this configuration.
If that does not work, we will need to evaluate the DSI input further based on this portion of the debug flow diagram (DS90UB941AS-Q1 DSI Bringup Guide):
In the case the new code and sequencing is unsuccessful, we may try to evaluate the DSI configurations and continuous clock by checking this section:
I have linked this guide above as well, please let me know if you need any further details testing this.
If the code and sequence works, we can try the next step which is to use the same code but with external timing input:
This code will then determine if all SoC configurations are coming into the 941 correctly.
If you have any further questions or concerns, please let me know.
Best,
Miguel
1、I configured the register of 941 to output the screen of 1920*1080 through the 948 unstring chip. At present, the screen always appears and the register read through the address of the 948 unstring reader always returns STATUS_I2C_RECEIVED_NACK, but the color bar chart can be displayed through the configuration of 941.
2、948 is set to 0V and R2 is set to 10kΩ. According to the specifications, IDx should be 0x2C. However, I directly connected the MCU to the i2c interface of 948 to read the register of 0xF3 using the address 0x2C, and the return value was STATUS_I2C_RECEIVED_NACK. Using IDx as 0x0C to read the register of 0xF3 does return a successfully readable value, what is the reason? Normal 948 address should be 0x2C, checked the hardware can not find the reason
3、This is the 941 schematic:
4、This is the 948 schematic:
2、Are you able to provide waveforms to certify the incoming clock and data to the RX is meeting 941AS specifications?
This is the waveform of the 941 RX,
MIPI-CKN to GND test
3、The comparison diagram displayed on the 1920*1080 display after stringing through 941/948 is as follows. The graph displayed after stringing through is stretched horizontally and vertically with different regular deformations
Hello,
clock-frequency = <148500000>;
hactive = <1920>;
vactive = <1080>;
hback-porch = <148>;
hfront-porch = <88>;
hsync-len = <44>;
vback-porch = <4>;
vfront-porch = <36>;
vsync-len = <5>;
pixelclk-active = <0>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
1、Continuous DSI CLK
2、Single DSI input, dual output
3、Not alternate line 3D mode
4、4 Number of DSI channels
5、DSI rate (Mbps)： 290Mbps
With the PCLK of 148.5 MHz and 4 data lanes, I believe the DSI frequency should match the following:
fDSI = (fPCLK * 4) / 12 = 148.5 MHz * 3 = 445.5 MHz
DSI Datarate = fDSI x 2 = 891 Mbps
In this case, the TSKIP calculation would be
TSKIP_CNT = Round(65 * 0.4455 GHz - 5) = 24
Can you try configuring the SoC to output this 891 Mbps data rate per lane, and also change this Tskip value?
Since the clock is continuous, I am assuming that the SoC is outputting in Non-burst mode, please correct me if I am wrong - there is a different configuration needed entirely for Burst mode.
Best,
Miguel
