This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN75DP130: aux bus disconnected on some powercycles (DP source mode default register settings)

Part Number: SN75DP130

Hi,

We experience issues with the propagation of the aux_src to aux_snk signals.
The setup is a custom monitor with an internal dp input connected through a 20 cm dp 1.2 cable to a video decoder dongle.
This dongle has a xilinx virtex fpga dp 1.2 4 lanes source connected to the dp130.
All dp130 register settings are default.
The test is to powercycle the monitor and check if the link is trained.

In 10% this fails because the dp driver is unable to write to dpcd 0x600 register in the sink and the driver doesn't continue to link training.
The driver first tries to put the sink in normal power state, read the dpcd registers and read the edid before starting link training.
So if the aux communication fails, there's no active differential signal from the fpga to dp130.
When the problem occurs, we notice that we see the manchester signal on the aux_src lines and this corresponds to writing 0x600.
However, we don't see any activity on the aux_snk, so it's as if the dp130 is not connecting them.
We have verified there are no glitches on the cad_snk signal, we just have a 1M pull down connected.
So the dp130 is not in tmds mode.

We have verified the vcc voltage and ramp up and check the rstn signal just after the voltage ramp up.
This all looks fine and in line with the datasheet.

We have tried to disable the squelch detection and autopowerdown, but no improvement.

What is strange is that the aux communication can be recovered by simply unplugging and replugging the dp cable, or even by shorting the hpd line for a few seconds.
So it's looks like the dp130 is stuck in some illegal state and is recovered by a hotplug.

We have also noticed that there are some consistent differences in the i2c register map between a good and bad powercycle:

good powercycle:

     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 00 01 00 12 04 00 00 00 00 00 00 00 00 00 00 00    .?.??...........
10: 00 00 00 00 00 08 08 00 00 14 00 00 00 00 00 00    .....??..?......
20: 01 00 30 14 36 36 f0 21 00 00 00 00 00 00 00 00    ?.0?66?!........
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

bad powercycle:

     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 00 01 00 12 04 00 00 00 00 00 00 00 00 00 00 00    .?.??...........
10: 00 00 00 00 00 08 08 00 00 00 02 00 00 00 00 00    .....??...?.....
20: 01 00 30 14 36 36 00 01 00 00 00 00 00 00 00 00    ?.0?66.?........
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

Notice how addresses 0x19 0x1a 0x26 and 0x27 differ.
These are all TI_TEST reserved registers according to the datasheet.
These are probably indicating what he root cause is, but unfortunately, these registers are not described in detail.

One last important thing to mention is that due to the power sequencing of the monitor, the main board is powered first and the decoder dongle seconds later.
This results in the dp hpd to be asserted already even before the dp130 is powered and the hpd remains asserted all the time.
Does the dp130 proper operation rely on seeing a hpd pulse after power up?

Thanks for your swift reply!

Br,

Bart

  • enginner is assigned for this issue, you will get reply soon.

  • Bart

    Do you have a scope capture of the power cycling sequence?

    If VCC ramps up, RSTn being hold low for 400ms and then driven high, and then EN ramps up, do you still see this issue?

    Thanks

    David

  • Hi David,

    I attached our schematics.

    Unfortunately we have no control over the EN pin which is connected to VCC through 0R resistor.

    The rstn is connected through 1uF capacitor to ground.

    I will make a scope capture of the VVC and rstn power up.

    Do you have any idea what the difference in register values between a good and bad cycle tell us?

    Br,

    Bart

  • I attached the requested scope images.

    I believe this rstn is in accordance with datasheet SLLSE57E.

    We really need a fix through some i2c register accesses as this decoder is in the field for several years already and we cannot make any board/bom changes at this point.

  • Bart

    Thanks for the scope capture and schematic.

    I did verify that this is an issue with couple flops inside the DP130 internal HPD controller being initialized to the wrong state during power up, and this in turn, produce an incorrect internal EN signal which would impact the AUX communication.

    The issue does not impact every DP130, only few units will be impacted by it.

    Unfortunately, the only workaround is to toggle the external HPD_SNK to clear this issue.

    Thanks

    David

     

  • Hi David,

    That's unfortunate, but at least it's a clear answer which confirms our experiments.
    We will look into delaying initial HPD assertion until considerably after DP130 power-up to make sure it sees a high-going level.

    Thanks for your effort.

    Best regards,

    Bart

  • Hi David,

    We have received new fw from the monitor mainboard colleagues which now issue a hpd low going pulse of 100 ms, 10 seconds after applying dp130 power.
    We're still able to reproduce the same issue.

    Does the hpd pulse need to be longer or are we missing something?

    Br,

    Bart

  • Hi David,

    Furthermore, we now disable the squelch detection and autopowerdown in the driver:

            dpv2_dp130_write_reg(dev, 0x01,  0x03); // Disable autopowerdown when hotplug goes low
            dpv2_dp130_write_reg(dev, 0x03,  0x08); // Disable squelch detection

    Do we need to remove this for the workaround to work or what is your recommendation regarding these settings?

    Br,

    Bart

  • Bart

    Squelch detection would only impact the main link, disabling the squelch detection would not impact the AUX traffic from the source to the sink.

    You can disable auto power down, this would impact the power consumption.

    Are you still seeing AUX not going through the DP130 even with the HPD toggle? Are you toggling the HPD_SNK? And if you manually unplug and plug the cable, are you able to get AUX going through the DP130?

    Thanks

    David

  • Hi David,

    Yes, we still see that the aux is not going through the dp130 with a 100 ms hpd toggle of HPD_SNK.
    Unplug and replugging the cable does fix the blocked aux.

    Br,

    Bart

  • Hi David,

    The behavior observed is not consistent: sometimes the dp130 needs a soft reset first (i2cset -y -f <bus #> <device address> 0x1b 0x80) and then a hpd pulse or cable unplug-plug to restore proper aux communication.
    Does this sounds logical to you?

    I'll try to soft rest the dp130 whenever we detect a long hpd pulse (>= 1000 ms), this way in the monitor, it should first get a soft reset followed by a high going hpd_snk.

    Are there any known issues around the soft reset?
    We don't want to create regression for other working use cases.

    Br,

    Bart

  • Hi David,

    As this is a known issue

    "I did verify that this is an issue with couple flops inside the DP130 internal HPD controller being initialized to the wrong state during power up, and this in turn, produce an incorrect internal EN signal which would impact the AUX communication."

    I have to insist in asking if you have more information about this issue and the way to workaround it.
    My suspicion is that the problem is caused by the hpd_snk being asserted already when the dp130 is powered and never toggles.
    Can you confirm this?
    If this is the case, unfortunately, it doesn't seem like we will be able to postpone the initial hpd assertion from the monitor mainboard.

    Br,

    Bart

  • Hi David,

    I have a seemingly working workaround:

    Monitor mainboard issues hpd pulse of 1000 ms after 10 secs of power to dp130.
    In the driver we detect the falling edge of the hpd and issue a dp130 soft reset.
    Just after the rising edge of the hpd the aux communication is restored.

    I hope to get some confirmation from you that this is a good approach or what it should be.

    We now still face a lot of partially automated testing for regression so fingers crossed.

    Br,

    Bart

  • Bart

    My suspicion is that the problem is caused by the hpd_snk being asserted already when the dp130 is powered and never toggles.
    Can you confirm this?

    This is correct. HPD being high when the DP130 powered up could result in the flops inside the HPD controller get set to the wrong state and not producing the correct internal EN signal.

    The workaround we tried was to unplug/plug the cable to produce a transition at HPD_SNK and verified this fixed the issue. We don't need to issue a reset to fix this issue. But I don't see an issue with your proposed workaround. 

    Are you seeing the issue on every DP130? 

    Thanks

    David

  • Hi David, 

    I think that could be a normal condition to have a connected monitor powered before the DP130, so if in this case what the steps to take to avoid problems?

    It's enough to issue a soft reset?

    Obviously unplug/plug the cable is not always a feasible solution.

    Regards

  • Bart

    Unfortunately, a soft reset by itself does not fully resolve the problem because the issue is within the flop inside the HPD controller logic. 

    Do you see the issue consistently with certain DP130? 

    Thanks

    David

  • Hi David,

    Please note that I didn't pose the last question on the forum, that was another person named ACM.

    It's my experience that we need to unplug (high -> low hpd); soft reset; plug (low -> high hpd) to fix the problem in all cases.
    In most cases unplug plug was enough to fix the problem, but not all.
    A soft reset by itself had no noticeable influence on the problem at all.

    I have not had the time to test a bunch of devices so I cannot give you any statistics.
    I was hoping that TI could provide these statistics as this is a known issue and it was mentioned that some devices are affected and others not,
    but without any further specifics.

    We were able to successfully work around this issue in our monitor with board to board dp connection as we have control over the hpd.
    But we also use the same decoder with externally connected monitors, so it's likely that we're getting or will be getting failure reports from the field.
    So I was also hoping for a better solution that works in all use cases, but there doesn't seem to be one?

    Br,

    Bart

  • Bart

    Since not all units will have this HPD issue, I am wondering is it possible that we can swap out the units that have this HPD issue?

    Do you also have the ability of changing the power sequence so the 1.1V comes up before the 3.3V?

    But you are right, for the units that have this problem, a soft reset will not fix the issue. A HPD unplug/plug and/or a soft reset will fix this issue.

    Thanks

    David

  • Hi David,

    This decoder has been in the field for several years.
    Our policy is to replace in warranty if a device is returned and the problem is hardware related.
    I have no view on how many devices have been swapped already for such issue.

    Do you have any idea on the statistics of affected ics?

    We have the SS device stuffed, so we cannot change the power sequence.

    Br,

    Bart

  • Bart

    Unfortunately, I don't have the statistics of the ICs being affected by this issue.

    When this issue was initially debugged, we noticed that when the power up sequence is being properly followed, the good units will always be good units and bad units will always be bad units. So my expectation is that once the bad unit is being replaced, you will not see the issue again on that particular decoder.

    Thanks

    David