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DS92LV18: Timing issue with serializer/deserializer circuit

Part Number: DS92LV18

Hi

I have a problem with a design I made with the DS92lv18 serializer/deserializer.

I will use this IC to make a serializer / deserializer via a fiber link using 2 identilcal boards. One in each end of the fibre, So data sent from one board will be outputtet on the other board and vice versa.

Right now i am testing making a loopback electrically.

 The circuit itself works fine until i add the fiber link then wierd things happens. It looks like a timing issue.

when the loopback is electrical it works. Data getting into the board on a specific input (1 of 18) comes out on the correct output.

For instance if a 100khz square wave is inserted on input 3 I measure a 100khz on output 4. and so on.

When I replace the electrical link with a fiber link. the signal on input 3 is also measured on output 4 and 5 and not only on output 3. I am not sure what this is?

The lock signal is stable and shows a valid link?

I have chased this problem for a while and am running out of ideas. Please help. 

Thanks

I have added a pdf of my design for info.

diagram MUX18 - 181019-01C.pdf

I have had contact with TI support - case number CS0110106 in December 2019

Thanks in advance

  • Hi,

    Most FO Transceivers do require some data encoding to ensure a minimum number of transitions and maintain a DC balance between 0 and 1 logic states.

    Have you tried to run the sync pattern through the FO Transceiver?

    How do the FO specs align with your data patterns?

    Regards,

    Lee