I did strap RX_CTRL to 5K76 PU & 2K49 PD (mode 3). Autonegotiation failed.

I am using Xilinx Ultrascale+ connected to

dp83867 RGMII.

Can you give example settings I need for 100BT. Datasheet is very confusing what mode needed for it.

Hi Raja,

I am from Aniruddha's team and will be stepping in to support you on this issue. When you say auto-negotiation fails, does that mean you are not seeing a link? Or are you linking at an incorrect speed? Can you read back register 0 and let me know the results?

Additionally, do you want to force 100 Mbps or let the device auto-negotiate to 100 Mbps?

Thank you,

Nikhil

Hi Raja,

Are you still seeing issues here?

Thank you,

Nikhil

Nikhil

Yes. I tried strap settings as per datasheet, Xilinx Eval board Z106, etc.

I tried to debug LwIP echo server code. It is trying to write to registers and failing to write into.

We have 2 identical 100BT ethernet port with 2 of TI Phy chips. They both tied with same MDIO.

I disabled 2nd Phy by keeping its reset LOw.

I read the Phy address different than set for.

If you have example Phy strap settings I will try them.

Thanks

Raja

Hi Raja,

Under the Description and Parametrics tab of the DP83867IR product folder, there is an EVM User guide that provides a schematic you may refer to. There is also a reference guide under the Design and Development tab of the product folder. Page 41 of the schematic will show you example strap connections. 

The only pin that requires a strap is the RX_DV/RX_CTRL pin. This pin must be strapped to mode 3 or mode four as described by the datasheet. 

Can you share your schematic with me?

Thank you,

Nikhil

Nikhil

Yes we strapped both to mode 3 and auto-neg not enabled. Just I am checking how the auto-neg is coded in Xilinx app.

I let you know if bug found in code. MDIO reading the address.

Raja

Hi Raja,

You mentioned you don't see the correct PHY address. What address do you see? Can you read the registers for by accessing the incorrect PHY address? If so, could you please read back registers 2,3,6E, and 6F?

Thank you,

Nikhil

Hi Raja,

Additionally, does the Xilinx Ultrascale have any internal pulls? This may impact the voltage on the strap pins. What is the pull-up on the MDIO line?

Thank you,

Nikhil