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PCA9548A: What will happen if the Trst is less than 500ns

Antony Fu
Expert 3345 points
Part Number: PCA9548A

Hello team,

We are looking for one issue of PCA9548A, and just found the delay time between REST and SDA is less than 500ns, 500ns is our spec, so what's will happen if Trst is less than it?

Thanks,

Antony

  • 0
    TI__Expert 3345 points

    Input more information about this case.

    we are the second source, and the first source is NXP's PCA9548, current the Rest pin is tied to VCC through one 4.7k pull-up, and the I2C pull up is VCC too.

    The spec of Trst is different for both parts,  the min value is 500ns for NXP part, but our max value is 500ns.

    current the system reports the error sometimes, this is caused by PCA9548A, and it goes away if replaced by NXP's part, so we are still checking the root, we are not sure whether this is the issue.

    Thanks.

    Antony

  • 0 in reply to Antony Fu
    TI__Guru 53575 points

    Hi Antony,

    Reset time (SDA clear) is defined to have a Max value of 500ns between a valid LOW assertion on #RESET and the SDA pin being asserted HIGH. This is specified as a propagation delay time and is therefore considered to be desirable to be short. We specify a maximum delay of 500ns to describe worst-case operating conditions such that the system can expect actual behavior to be at or less than this delay value. Delay times shorter than 500ns are normal.

    Could you share more information on the error that the system reports? I don’t think it is likely that the Trst specification would cause an issue unless #RESET was being asserted during an I2C packet (in which case the slower response time of NXP’s device may make a difference).

    Regards,
    Eric

  • 0 in reply to Eric Schott1
    TI__Expert 3345 points

    HI Eric,

    We got more information from customer, customer found it has relation with the I2C operation, the solution 1  causes can't find the device after PCA9548, and solution 2 has no problem.

    But NXP's 9548 work well with solution 1 and solution 2.

    Thanks,

    Antony

    i2c-JBOD_SBOM.PPTX

  • 0 in reply to Antony Fu
    TI__Guru 53575 points

    Hi Antony,

    Thank you for the logic analyzer shots and the solution you found. I believe this is by design for PCA9548A. The written channels will only become active after a stop condition is recognized by the device. This ensures stability on the downstream channels when they are activated. If these channels were to activate while the bus was not idle, noise could propagate and cause errors in downstream devices. This is outlined in section 8.6.2 of the datasheet. 

    Please ensure a stop condition is always generated after writing to the control register bits.

    Regards,
    Eric