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Original question:

DS90UB948-Q1: AC decoupling capacitor values when interfacing with 941 VS 947 serializers

DS90UB948-Q1: DS90UB948-Q1

Pradeepkumar Selvaraj1
Prodigy 200 points
Part Number: DS90UB948-Q1
Other Parts Discussed in Thread: DS90UH949A-Q1, DS90UB921-Q1, DS90UB947-Q1

Hello,

Regarding this DS90UB948-Q1 deserializer, I have designed FPD III to OLDI deserializers for LVDS, RGB, HDMI signals.

Totally three different deserializers in my design, for three serializers inputs (DS90UB947-Q1 for LVDS; DS90UH949A-Q1 for HDMI; DS90UB921-Q1 for RGB) which are coming from a vehicle dashboard silver box unit.

I am attaching the schematic of my design and would like to have your review comments and/or any suggestions.

Thanks in advance.

Regards,

Pradeep. S

  • 0
    TI__Genius 12866 points

    Hi Pradeep,

    I will review the schematic and get back to you within one week.

    Best Regards,

    Charley Cai

  • 0 in reply to Charley Cai
    TI__Genius 12866 points

    Hi Pradeep,

    1. You shouldn’t tie BISTEN to 3.3V by default otherwise the device will stuck in BIST mode. Please DNP the R28 and populate R1098.
    2. Suggest using 100nF on RIN+ and 47nF on RIN- for compatibility with all three serialziers.
    3. I didn’t see I2C_SCL and I2C_SDA pull up from attached schematic. Could you confirm that they are pulled to 3.3V or 1.8V?

    Best Regards,

    Charley Cai

  • 0 in reply to Charley Cai
    Prodigy 200 points

    Hi Charley Cai,

    Thank you very much for your valuable comments!!

    I will implement the comments in schematic. 

    And, I2C SCL & SDA are pulled up to 3.3V, but is not shown in this schematic page.

    BTW, I have arrived to a quick query when referring to the layout guidelines and Eval schematics.

    In Datasheet, It suggests power input pin caps must be at least 5 times the input supply used (in 10.1 Layout Guidelines section). But we observed from the EVAL board schematics that for bulk cap (C54) 10uF, 6.3V part is used for power rail VDD pins as shown in attached image. 

    As of now, I have chosen the capacitor voltages about 3 times the power rail voltage. Is it okay?

    Please suggest your opinion about this.

    Thanks & Regards,

    Pradeep. S

  • 0 in reply to Pradeepkumar Selvaraj1
    TI__Genius 12866 points

    3x time should be ok.

    Best Regards,

    Charley Cai

  • 0 in reply to Charley Cai
    Prodigy 200 points

    Hi Charley,

    Thank you for clarifying. we have implemented the comments and arrived to layout.

    Could you please provide the EYE opening details for FPD link input lines and OLDI output lines as we are running post layout simulation now.

    Requesting for your support. Earliest response will helps us a lot since we are at delivery stage.

    Thanks

    Pradeep. S

  • 0 in reply to Pradeepkumar Selvaraj1
    TI__Genius 12866 points

    Hi Pradeep,

    The spec can be found the in the 948 datasheet electrical spec section.

    Look for FPD-LINK III INPUT and OLDI DRIVER for the DC spec.

    look for Switching Characteristics for OLDI AC spec. 

    FPD-Link link input jitter should be less than 0.3UI.

    Best Regards,

    Charley Cai