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Original question:

SN65DSI86: SN65DSI86 does not support HDCP, could not use for external DP monitor?

SN65DSI86: Using external DP monitor

Eduardo Teofilo
Prodigy 20 points
Part Number: SN65DSI86
Other Parts Discussed in Thread: TEST2

Hi,

I saw on other thread that if we want to use SN65DSI86 with a DP monitor is necessary TEST2 to be pulled high.

We are on the same scenario of the following thread  https://e2e.ti.com/support/interface/f/138/t/853036?keyMatch=SN65DSI86&tisearch=Search-EN-support

Could you explain why TEST2 need to be pulled high?

We are not able to add the pull up to TEST2 because is tied directly to GND. There is a workaround to enable DP without pulling high TEST2?

disabling ASSR is not enough?

  • 0
    TI__Guru**** 176171 points

    Hi,

    The ASSR is enabled by default. To disable ASSR, TEST2 pin must be pulled high to enable register read/write control to disable the ASSR.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 20 points

    Hi David,

    Ok, so according with the datasheet register 0x5A bits 1:0. mention that what is changing is the seed value (wich by the way is the same for both modes)  not enable or disable R/W.

    Could you tell me which bit is not able to read/write when TEST2 Pin is tied to ground?

    Also if you can share the documentation where is described what you mention on your reply would be helpful.

    Regards,

    Eduardo

  • 0 in reply to David (ASIC) Liu
    Prodigy 10 points

    I have the same question.

    You are saying that the TEST2 pin must be pulled high to enable register read/write.

    The only bits that are blocked by this are the following:

    ASSR_CONTROL. This field controls the scrambler seed used. Standard DP scrambler seed value is 0xFFFF. The ASSR seed value is 0xFFFF.

    This field is R/W if TEST2 pin is sampled high on rising edge of EN and bit 0 of offset 0x16 in Page 7 is set. Otherwise this field is readonly.

    00 = Standard DP Scrambler Seed.

    01 = Alternative Scrambler Seed Reset (Default)

    10 = Reserved.

    11 = Reserved.

    This doesn't say that it disables ASSR, it only says that a different seed is used, and it is the same.

    Could you please explain? My hardware does not have TEST2 accessible and I need alternatives.

    Thanks!

  • 0 in reply to Jose Ogando
    TI__Guru**** 176171 points

    Hi,

    ASSR_OVERRIDE is on Page 7 Register 0x16

    When TEST2 is low, ASSR_OVERRIDE is read-only. When TEST2 is high, ASSR_OVERRIDE is read/write.

    To disable ASSR

    <?xml version="1.0"?>

    -<aardvark>

    <configure pullups="0" tpower="1" gpio="0" spi="1" i2c="1"/>

    <i2c_bitrate khz="100"/>
    ======Page 7======
    <i2c_write radix="16" count="1" addr="0x2D">FF 07</i2c_write>
    /> ======ASSR Control to RW from R-only. TEST2 pin must be high at rising edge of EN pin ======
    <i2c_write radix="16" count="1" addr="0x2D">16 01</i2c_write>
    /> ======Page 0======
    <i2c_write radix="16" count="1" addr="0x2D">FF 00</i2c_write>
    /> ======enhanced framing enable. NO ASSR ======
    <i2c_write radix="16" count="1" addr="0x2D">5A 04 </i2c_write>
    />
    </aardvark>

    Thanks

    David