DP83822I: DP83822I layout guidelines

Hello GZ,

Thank you for you questions. The MAC interface signal pins may be more susceptible to noise so placing them close to the MAC is important. 

Differential MDI traces 5-6cm in length to the magnetics are within our recommended layout guidelines. 

Our entire design and layout guide can be found in SNLA079: http://www.ti.com/lit/an/snla079d/snla079d.pdf

Regards,

Justin 

Thanks, Justin

My doubt, even reading your guide:  in the path towards the connector the differential  signal is forced to unbalance (the diff signal is forced to split twice towards the connector pin ), it also faces

several discontinuities (two soldering, two connector joints, and the short (3-4cm) flat cable - which cause unpredictable reflections and unbalance), impedance mismatch and at least two plane split + the cable that does not see a plane  below..

In the light of the fact that our target speed is 100MB/s (maximum speed for our MAC)  considering that the MAC cannot be moved to the lower plane,  wouldn't it be easier to keep in check with a diligent layout ( supported by physical simulations) a series of unbalanced lower frequency signals?

That's the classic too-short blanket problem:-)

Moving the MAC to the lower plane is not possible for US.

Regards,

GZ

Hello GZ,

You may be correct if the you cannot meet the layout guidelines and see many more discontinuities and split planes on the differential signal traces than a 4 or 6 layer board would require. 

Please note that the layout guidelines are provided to help avoid common issues and protect the signal path integrity of both the MDI and MAC. You can take careful consideration of the layout using a two layer board but I can't provide assurance that careful layout will mitigate the concerns.

I think your analysis is correct and the use of simulation will yield the best results. 

Regards,
Justin 

Ciao Justin, 

thank you for your reply...

Let me clarify more: the phys is plit between two boards, not two layers ... The diff pair is sent to the other board via a connector and a small flat cable with the great deal of discontinuities I told you before.

My question is ( considering that we cannot do otherwise) if, according to your expertise,  it is easier keeping in check ( taking some riscs, be clear:-) )  the low frequency MII/RMII  unbalanced signals rather than the delicate balanced ones. We might move the phys device in the other board sending  with the utmost care the MII signals to the MAC device via connector and flat cable.

What do you think about that?

Regards,

G

Hi GZ,

Thank you, I understand now. Yes, it would be better to keep the PHY and differential MDI signals to the cable terminal on the same board and MII signals can be sent through the connector to another board.

Regards,
Justin 

Ciao Justin,

Thank you for your confirmation.

I was studying your DP83822EVM evaluation module, it seems pretty in line with what we 've been discussing so far.

The board does not integrate any MAC, so an additional board providing all the necessary MAC signals  (via connector J14) is required.

Can you confirm that?

Can you indicate the complete setup  for this EVM ?

Other question:

If you give a look at the top layer (fig 21 page 24) , the differential signals (in their path towards magnetics)  actually cross several layers via some vias,  this seems to contradict the layout guidelines.  

Plus, R27, R38, R39, R40 are placed at the bottom close to the magnetics, this isn't unclear too..

Can you give me your valuable opinion on the matter?

Thanks again

G.

DP83822EVM.pdfSee is neede

Hi GZ,

That is correct, we do not have an on-board MAC for the DP83822EVM, allowing various different MAC or Processors to be used. You can also find reference design with MAC connections in the design documentation.

The MDI signals are sent along a single layer but need to be routed to the top or bottom of the board to connect to the surface mount components like magnetics and terminal connector. 

Regards,

Justin 

Thanks Justin,

This is perfectly in line with what we are considering to do.

Can you confirm that this solution can go full speed?

Regards,

G

Thank you Justin.

Last question (sorry but I missed It before) can you see any troubles with the RMII interface (less signal count but  high frequency clock) over the external connectors?

This would allow us to better exploit the connections between the two boards.

- G