DP83867E: Yes

Onur Kusakoglu

Part Number: DP83867E
Other Parts Discussed in Thread: DP83869HM, DP83869

Hello,

We would like to have an Ethernet communication on our board. Our selected FPGA is Intel Arria-10 and we would like to use TI PHY DP83867E.

IO communication needs to be at 1.8 voltage level. But there is an incompatibility on IO levels at 1.8V level.

Maximum input low the TI PHY can accept is 0.2 × VDDIO which is 0.36V, on the other hand FPGA Outout Low(max) can go up to 0.45V at 1V8 level.

So basically Arria-10 can send 0.45V signal and thinks it is low but for TI Phy this is not a low signal.

My first question will be, maximum input low for TI chip 0.2xVDDIO is accurately tested?

Do you have any suggestion for solution?

Best Regards

Onur Kusakoglu

over 4 years ago

0 Justin Lazaruk over 4 years ago

TI__Expert 7040 points

Hi Onur,

What is the current load IOL that is specified for the VOL of 0.45V? I've attached a previous e2e post answering a similar question regarding the VOL VIL mismatch between PHY and processor.

https://e2e.ti.com/support/interface/f/138/t/551387

Regards,

Justin

0 Onur Kusakoglu over 3 years ago in reply to Justin Lazaruk

Intellectual 960 points

Hi Justin,

It is 2mA.

I checked the link you have provided, PHY max VIL is 0.6V in any case or it is related the current load of the driver?

0 Onur Kusakoglu over 3 years ago in reply to Onur Kusakoglu

Intellectual 960 points

Good morning,

I am still waiting a response :)

Discussion is a bit hot here.

0 Justin Lazaruk over 3 years ago in reply to Onur Kusakoglu

TI__Expert 7040 points

Hi Onur,

I cannot find the data used to show the DP83867 will accept a VIL of 0.6V referenced by Rob in the attached e2e document. What Rob was referring to is the VIL specification is set to be compliant to JEDEC 8-5A but will tolerate a higher VIL than JEDEC requires.

I also expect CMOS IOs of the Intel Arria FPGA to swing from rail to rail and be below the 0.2*VDDIO VIL specified on the datasheet. You can check this using a signal integrity tool and DP83867 IBIS model.

Regards,
Justin

0 Onur Kusakoglu over 3 years ago in reply to Justin Lazaruk

Intellectual 960 points

Hi Justin,

Unfortunately, I dont have a signal integrity tool. What Intel states in their data sheet is V(ol) is 0.45V at current strength is 2mA.

I am wondering how Rob came up with the 0.6V, is it maybe at a certain level of drive current?

Best regards,

Onur Kusakoglu

0 Justin Lazaruk over 3 years ago in reply to Onur Kusakoglu

TI__Expert 7040 points

Hi Onur,

The DP83867 does have margin in the VIL specification, such that it can support a VIL of 0.6V. Rob is correct.

However, the DP83869HM device is a similar device that will guarantee the VIL up to 0.630V at VDDIO=1.8V, as per the datasheet. I recommend selecting this device.

Regards,
Justin

0 Onur Kusakoglu over 3 years ago in reply to Justin Lazaruk

Intellectual 960 points

Hi Justin,

This is good news. Is there any test result or any data sheet update regarding this will be shared?

I will also check DP83869HM data sheet. What is important for us I can think by heart now is

1-) RGMII and SGMII support from first look it is there,

2-) IEEE 802.3 standard but do not remember exact revision or addition if there is even one.

3-) RGMII and SGMII latency

4-) Is pinout different? I can also check

5-) Max working Junction temp are both 125 C as far as I can see.

basically FW is already developed with DP 83867E.

If you have further info or comparison table I would appreciate.

0 Justin Lazaruk over 3 years ago in reply to Onur Kusakoglu

TI__Expert 7040 points

Hello Onur,

We will not be updating the VIL specifications in the DP83867 datasheet.

The pinout for DP83867 and DP83869 is different but the register maps are mostly shared. Both devices are rated to 125C and have very low latency.

Regards,
Justin

0 Onur Kusakoglu over 3 years ago in reply to Justin Lazaruk

Intellectual 960 points

Hi Justin,

Thank you very much for the help so far.

So we will be using the DP83867. We have proved our FW and did connection test with this component.

Since DP83867 has VIL max at 0.6V, I don't see any other issue not to use it.

If you also can share, from where you have got this 0.6V, I'd be more appreciated.

PS: For your info also Xilinx Ultrascale+ MPSOC devices are not compatible with VIL(max) as stated in DP83867 data sheet at 1V8 level.

Best Regards

Onur Kusakoglu

0 Justin Lazaruk over 3 years ago in reply to Onur Kusakoglu

TI__Expert 7040 points

Hi Onur,

The DP83867 VIL up to 0.6V that Rob referred to is based on silicon validation data.

Thank you for that information. I will look into the Xilinx Ultrascale FPGA products to review their VDD conditions.

Regards,
Justin

0 Onur Kusakoglu over 3 years ago in reply to Justin Lazaruk

Intellectual 960 points

Thanks.

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DP83867E: Yes