Hi Team,
We are connecting FPD link III camera to RIN0+ & RIN0- of the chip ,so we have a few queries:
1)Based on certain limitations on the processor side so we have to connect only two lanes of the CSI-2 output.Need confirmation on whether this is possible.
2)If only two lanes are connected CSI_D0P/N & CSI_D1P/N which clock lines are to be considered.CSI_CLKOP/N or CSI_CLK1P/N?
3)Is CSI_CTL Register[5:4] setting alone enough for the deserialiser to operate in CSI-2 two lane mode or any other hardware settings are to be considered?
Please let us know your suggestions on this at the earliest.
Thanks,
Bharath
